_primary.vhd

来自「fpga功能实现有限字长响应FIR」· VHDL 代码 · 共 9 行

library verilog;
use verilog.vl_types.all;
entity mux_h is
    port(
        i               : in     vl_logic_vector(2 downto 0);
        h               : out    vl_logic_vector(7 downto 0)
    );
end mux_h;