_primary.vhd

来自「fpga功能实现有限字长响应FIR」· VHDL 代码 · 共 38 行

library verilog;
use verilog.vl_types.all;
entity top is
    port(
        reset_ini       : in     vl_logic;
        clk1            : in     vl_logic;
        clk2            : in     vl_logic;
        \in\            : in     vl_logic_vector(7 downto 0);
        \out\           : out    vl_logic_vector(18 downto 0);
        x0              : out    vl_logic_vector(7 downto 0);
        x1              : out    vl_logic_vector(7 downto 0);
        x2              : out    vl_logic_vector(7 downto 0);
        x3              : out    vl_logic_vector(7 downto 0);
        x4              : out    vl_logic_vector(7 downto 0);
        x5              : out    vl_logic_vector(7 downto 0);
        x6              : out    vl_logic_vector(7 downto 0);
        x7              : out    vl_logic_vector(7 downto 0);
        x8              : out    vl_logic_vector(7 downto 0);
        x9              : out    vl_logic_vector(7 downto 0);
        x10             : out    vl_logic_vector(7 downto 0);
        x11             : out    vl_logic_vector(7 downto 0);
        x12             : out    vl_logic_vector(7 downto 0);
        x13             : out    vl_logic_vector(7 downto 0);
        x14             : out    vl_logic_vector(7 downto 0);
        x15             : out    vl_logic_vector(7 downto 0);
        x_i             : out    vl_logic_vector(7 downto 0);
        x_Ni            : out    vl_logic_vector(7 downto 0);
        x               : out    vl_logic_vector(8 downto 0);
        h               : out    vl_logic_vector(7 downto 0);
        P_i             : out    vl_logic_vector(16 downto 0);
        OE              : out    vl_logic;
        reset           : out    vl_logic;
        i               : out    vl_logic_vector(2 downto 0);
        part_sum        : out    vl_logic_vector(18 downto 0);
        sum             : out    vl_logic_vector(18 downto 0)
    );
end top;