dmatest.v.txt

基于Samsung2410平台的PCMCIA中的DMA测试程序和Wait程序

module DMATEST(clock,nReset,dmaMode,nDmaStart,nDREQ,nDACK,state);
    input clock,nReset;
    input nDmaStart;
//    input [1:0] dmaMode;	//remove by eric rong 2003-7-8
    input dmaMode;
    input nDACK;
    output nDREQ;
    output [4:0] state;
	
    reg nDREQ;
    reg enCounter;
    reg preset16,preset1;
    reg [4:0] state;
    reg [3:0] counter;
    reg snDACK;
    reg snDmaStart;

    parameter [1:0] HS16=1,WHOLE=2; //mode
    parameter [4:0] READY=0,HS0=1,HS1=2,HS2=3,HS3=4,
					HS4=5,WH0=6,FL0=7,DM0=8,ERR=9; 

    always @(posedge clock or negedge nReset) 
	begin 
	    if(!nReset)counter=0;
	    else if(enCounter)counter=counter-1;
	    else if(preset16)counter=0;
	    else if(preset1)counter=1;
	end
	
    //always @(negedge clock) //for more faster nXDREQ generation
    always @(posedge clock)   //because device is slow, negedge may not operate in 66Mhz
	begin
	    snDACK=nDACK;
	end

    always @(posedge clock)
	begin
	    snDmaStart=nDmaStart;
	end


//CAUTION:
//set dmaMode bits first. And then,set dmaStart bit.	
//After DMA is started, cleare dmaStart bit.
    always @(posedge clock or negedge nReset)
	begin
	    if(!nReset)
		state=READY;
	    else
		case(state)
		    READY: 
			if(!snDmaStart)
			    begin
				case(dmaMode)
				    HS16:state=HS0;
				    WHOLE:state=WH0;
				    default:state=READY;
				endcase
			    end
			else
			    state=READY;
		    HS0: state=HS1;
		    HS1:
			if(snDACK)
			    state=HS1;
			else
			    state=HS2;
		    HS2:
			if(snDACK==0)state=HS2;
			else state=HS3;
		    HS3:state=HS4; //counter--
 		    HS4:if(counter!=0)
			    state=HS1; //next DMA request.
			else begin
				if(!nDmaStart) //check dmaStart bit is cleared?
				    state=HS4; 
				else
				    state=READY;
			    end

		    WH0: state=HS1; 
		    FL0: state=FL0; //not implemented yet.
		    DM0: state=DM0; //not implemented yet.
		    default:state=ERR;
		endcase
	end


    always @(state)
	begin
	    preset16=0;
	    preset1=0;
	    nDREQ=1;
	    enCounter=0;
	    case(state)
		HS0:
		    preset16=1; 
		HS1: 
		    nDREQ=0;
		HS3:
		    enCounter=1;
		WH0:
		    preset1=1;
	    endcase
	end
endmodule