pc2fpga.v

this is a sample about usb out transmission

module pc2fpga  ( rst  ,
                  clk,
                             
                  fifo_wr ,
                  fifo_rd ,            
                  fifo_data,
                             
                  fifo_pf,
                  fifo_full,
                  fifo_empty,
                );
                
 input           rst     ;
 input           clk     ;
 input           fifo_pf,fifo_full,fifo_empty;
 
 input[7:0]      fifo_data ;
 output          fifo_wr   ;
 output          fifo_rd   ;
 
 
 //ports
 wire            rst     ;  
 wire            clk     ;  
 wire[7:0 ]      fifo_data ;                             
 reg             fifo_wr   ;  
 reg             fifo_rd   ;  
                              
 
 //internal signals
 reg             clkin;
 reg  [2:0]      STATE,NEXT;
 
 //parameters
 parameter     IDLE    = 3'D0,
               READ_1  = 3'D1,
               READ_2  = 3'D2;
               
 //Div clk by 2
 always @ (posedge clk or negedge rst)
 begin
   if(!rst)
      clkin <= 'b1;
   else
      clkin <= ~clkin;
 end 
 
 
 //state machine              
 always @ (STATE or rst)
 begin
     case(STATE)
     IDLE    :  NEXT = READ_1;
              
     READ_1 : if(!fifo_empty)
                   NEXT = READ_1;
               else
                   NEXT = READ_2;
     READ_2 :      NEXT = READ_1;
     default : NEXT = IDLE ;
     endcase
 end
 
 //registe the state
 always @ (posedge clkin or negedge rst)
 if(!rst)
    STATE <= IDLE;
 else
    STATE <= NEXT;
 
 
 always @ (posedge clkin or negedge rst)
 if(!rst)
    begin
        fifo_wr   <=1'b1;
        fifo_rd   <=1'b1;
    end
 else
    case(STATE)
    IDLE    : begin
                  fifo_rd     <= 1;
                  fifo_wr     <= 1;
              end
    READ_1 : begin
                  fifo_wr     <= 1'b1;
                  if(fifo_empty)
                     fifo_rd   <= 1'b0;
                  else
                     fifo_rd   <= 1'b1;
              end
    READ_2 : begin
                  fifo_wr  <= 1'b1;
                  fifo_rd  <= 1'b1;
              end
    endcase

  
endmodule