pc2fpga.map.qmsg

this is a sample about usb out transmission

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_mo8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_mo8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_mo8 " "Info: Found entity 1: cntr_mo8" {  } { { "db/cntr_mo8.tdf" "" { Text "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/cntr_mo8.tdf" 25 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_e29.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_e29.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_e29 " "Info: Found entity 1: cntr_e29" {  } { { "db/cntr_e29.tdf" "" { Text "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/cntr_e29.tdf" 25 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/lpm_compare.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/lpm_compare.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_compare " "Info: Found entity 1: lpm_compare" {  } { { "lpm_compare.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_compare.tdf" 262 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/comptree.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/comptree.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 comptree " "Info: Found entity 1: comptree" {  } { { "comptree.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/comptree.tdf" 102 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/cmpchain.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/cmpchain.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpchain " "Info: Found entity 1: cmpchain" {  } { { "cmpchain.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/cmpchain.tdf" 84 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altshift.tdf" 28 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/sld_acquisition_buffer.vhd 4 2 " "Info: Found 4 design units, including 2 entities, in source file c:/altera/quartus50/libraries/megafunctions/sld_acquisition_buffer.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_acquisition_buffer-rtl " "Info: Found design unit 1: sld_acquisition_buffer-rtl" {  } { { "sld_acquisition_buffer.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_acquisition_buffer.vhd" 73 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 sld_offload_buffer_mgr-rtl " "Info: Found design unit 2: sld_offload_buffer_mgr-rtl" {  } { { "sld_acquisition_buffer.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_acquisition_buffer.vhd" 308 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_acquisition_buffer " "Info: Found entity 1: sld_acquisition_buffer" {  } { { "sld_acquisition_buffer.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_acquisition_buffer.vhd" 46 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "2 sld_offload_buffer_mgr " "Info: Found entity 2: sld_offload_buffer_mgr" {  } { { "sld_acquisition_buffer.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_acquisition_buffer.vhd" 271 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_nt9.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_nt9.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_nt9 " "Info: Found entity 1: cntr_nt9" {  } { { "db/cntr_nt9.tdf" "" { Text "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/cntr_nt9.tdf" 25 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/lpm_ff.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/lpm_ff.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_ff " "Info: Found entity 1: lpm_ff" {  } { { "lpm_ff.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_ff.tdf" 46 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 425 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_th92.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_th92.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_th92 " "Info: Found entity 1: altsyncram_th92" {  } { { "db/altsyncram_th92.tdf" "" { Text "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/altsyncram_th92.tdf" 34 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_bv7.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_bv7.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_bv7 " "Info: Found entity 1: cntr_bv7" {  } { { "db/cntr_bv7.tdf" "" { Text "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/cntr_bv7.tdf" 25 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_dn7.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_dn7.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_dn7 " "Info: Found entity 1: cntr_dn7" {  } { { "db/cntr_dn7.tdf" "" { Text "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/cntr_dn7.tdf" 25 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_rom_sr-INFO_REG " "Info: Found design unit 1: sld_rom_sr-INFO_REG" {  } { { "sld_rom_sr.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd" 27 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_rom_sr " "Info: Found entity 1: sld_rom_sr" {  } { { "sld_rom_sr.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_AE_SUCCESSFUL" "auto_signaltap_0 " "Info: Analysis and Synthesis generated SignalTap II or debug node instance \"auto_signaltap_0\"" { { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|pc2fpga\|clkin acq_clk " "Info: Source node \"\|pc2fpga\|clkin\" connects to port \"acq_clk\"" {  } { { "../Src/pc2fpga.v" "clkin" { Text "D:/RedLogic/RCII_samples/USB_OUT/Src/pc2fpga.v" 31 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|pc2fpga\|fifo_data\[0\] acq_trigger_in\[0\] " "Info: Source node \"\|pc2fpga\|fifo_data\[0\]\" connects to port \"acq_trigger_in\[0\]\"" {  } { { "../Src/pc2fpga.v" "fifo_data\[0\]" { Text "D:/RedLogic/RCII_samples/USB_OUT/Src/pc2fpga.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|pc2fpga\|fifo_data\[0\] acq_data_in\[0\] " "Info: Source node \"\|pc2fpga\|fifo_data\[0\]\" connects to port \"acq_data_in\[0\]\"" {  } { { "../Src/pc2fpga.v" "fifo_data\[0\]" { Text "D:/RedLogic/RCII_samples/USB_OUT/Src/pc2fpga.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|pc2fpga\|fifo_data\[1\] acq_trigger_in\[1\] " "Info: Source node \"\|pc2fpga\|fifo_data\[1\]\" connects to port \"acq_trigger_in\[1\]\"" {  } { { "../Src/pc2fpga.v" "fifo_data\[1\]" { Text "D:/RedLogic/RCII_samples/USB_OUT/Src/pc2fpga.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|pc2fpga\|fifo_data\[1\] acq_data_in\[1\] " "Info: Source node \"\|pc2fpga\|fifo_data\[1\]\" connects to port \"acq_data_in\[1\]\"" {  } { { "../Src/pc2fpga.v" "fifo_data\[1\]" { Text "D:/RedLogic/RCII_samples/USB_OUT/Src/pc2fpga.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|pc2fpga\|fifo_data\[2\] acq_trigger_in\[2\] " "Info: Source node \"\|pc2fpga\|fifo_data\[2\]\" connects to port \"acq_trigger_in\[2\]\"" {  } { { "../Src/pc2fpga.v" "fifo_data\[2\]" { Text "D:/RedLogic/RCII_samples/USB_OUT/Src/pc2fpga.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|pc2fpga\|fifo_data\[2\] acq_data_in\[2\] " "Info: Source node \"\|pc2fpga\|fifo_data\[2\]\" connects to port \"acq_data_in\[2\]\"" {  } { { "../Src/pc2fpga.v" "fifo_data\[2\]" { Text "D:/RedLogic/RCII_samples/USB_OUT/Src/pc2fpga.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|pc2fpga\|fifo_data\[3\] acq_trigger_in\[3\] " "Info: Source node \"\|pc2fpga\|fifo_data\[3\]\" connects to port \"acq_trigger_in\[3\]\"" {  } { { "../Src/pc2fpga.v" "fifo_data\[3\]" { Text "D:/RedLogic/RCII_samples/USB_OUT/Src/pc2fpga.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|pc2fpga\|fifo_data\[3\] acq_data_in\[3\] " "Info: Source node \"\|pc2fpga\|fifo_data\[3\]\" connects to port \"acq_data_in\[3\]\"" {  } { { "../Src/pc2fpga.v" "fifo_data\[3\]" { Text "D:/RedLogic/RCII_samples/USB_OUT/Src/pc2fpga.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|pc2fpga\|fifo_data\[4\] acq_trigger_in\[4\] " "Info: Source node \"\|pc2fpga\|fifo_data\[4\]\" connects to port \"acq_trigger_in\[4\]\"" {  } { { "../Src/pc2fpga.v" "fifo_data\[4\]" { Text "D:/RedLogic/RCII_samples/USB_OUT/Src/pc2fpga.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|pc2fpga\|fifo_data\[4\] acq_data_in\[4\] " "Info: Source node \"\|pc2fpga\|fifo_data\[4\]\" connects to port \"acq_data_in\[4\]\"" {  } { { "../Src/pc2fpga.v" "fifo_data\[4\]" { Text "D:/RedLogic/RCII_samples/USB_OUT/Src/pc2fpga.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|pc2fpga\|fifo_data\[5\] acq_trigger_in\[5\] " "Info: Source node \"\|pc2fpga\|fifo_data\[5\]\" connects to port \"acq_trigger_in\[5\]\"" {  } { { "../Src/pc2fpga.v" "fifo_data\[5\]" { Text "D:/RedLogic/RCII_samples/USB_OUT/Src/pc2fpga.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|pc2fpga\|fifo_data\[5\] acq_data_in\[5\] " "Info: Source node \"\|pc2fpga\|fifo_data\[5\]\" connects to port \"acq_data_in\[5\]\"" {  } { { "../Src/pc2fpga.v" "fifo_data\[5\]" { Text "D:/RedLogic/RCII_samples/USB_OUT/Src/pc2fpga.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|pc2fpga\|fifo_data\[6\] acq_trigger_in\[6\] " "Info: Source node \"\|pc2fpga\|fifo_data\[6\]\" connects to port \"acq_trigger_in\[6\]\"" {  } { { "../Src/pc2fpga.v" "fifo_data\[6\]" { Text "D:/RedLogic/RCII_samples/USB_OUT/Src/pc2fpga.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|pc2fpga\|fifo_data\[6\] acq_data_in\[6\] " "Info: Source node \"\|pc2fpga\|fifo_data\[6\]\" connects to port \"acq_data_in\[6\]\"" {  } { { "../Src/pc2fpga.v" "fifo_data\[6\]" { Text "D:/RedLogic/RCII_samples/USB_OUT/Src/pc2fpga.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|pc2fpga\|fifo_data\[7\] acq_trigger_in\[7\] " "Info: Source node \"\|pc2fpga\|fifo_data\[7\]\" connects to port \"acq_trigger_in\[7\]\"" {  } { { "../Src/pc2fpga.v" "fifo_data\[7\]" { Text "D:/RedLogic/RCII_samples/USB_OUT/Src/pc2fpga.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|pc2fpga\|fifo_data\[7\] acq_data_in\[7\] " "Info: Source node \"\|pc2fpga\|fifo_data\[7\]\" connects to port \"acq_data_in\[7\]\"" {  } { { "../Src/pc2fpga.v" "fifo_data\[7\]" { Text "D:/RedLogic/RCII_samples/USB_OUT/Src/pc2fpga.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|pc2fpga\|fifo_empty acq_trigger_in\[8\] " "Info: Source node \"\|pc2fpga\|fifo_empty\" connects to port \"acq_trigger_in\[8\]\"" {  } { { "../Src/pc2fpga.v" "fifo_empty" { Text "D:/RedLogic/RCII_samples/USB_OUT/Src/pc2fpga.v" 15 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|pc2fpga\|fifo_empty acq_data_in\[8\] " "Info: Source node \"\|pc2fpga\|fifo_empty\" connects to port \"acq_data_in\[8\]\"" {  } { { "../Src/pc2fpga.v" "fifo_empty" { Text "D:/RedLogic/RCII_samples/USB_OUT/Src/pc2fpga.v" 15 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|pc2fpga\|fifo_empty trigger_in " "Info: Source node \"\|pc2fpga\|fifo_empty\" connects to port \"trigger_in\"" {  } { { "../Src/pc2fpga.v" "fifo_empty" { Text "D:/RedLogic/RCII_samples/USB_OUT/Src/pc2fpga.v" 15 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|pc2fpga\|fifo_full acq_trigger_in\[9\] " "Info: Source node \"\|pc2fpga\|fifo_full\" connects to port \"acq_trigger_in\[9\]\"" {  } { { "../Src/pc2fpga.v" "fifo_full" { Text "D:/RedLogic/RCII_samples/USB_OUT/Src/pc2fpga.v" 15 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|pc2fpga\|fifo_full acq_data_in\[9\] " "Info: Source node \"\|pc2fpga\|fifo_full\" connects to port \"acq_data_in\[9\]\"" {  } { { "../Src/pc2fpga.v" "fifo_full" { Text "D:/RedLogic/RCII_samples/USB_OUT/Src/pc2fpga.v" 15 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|pc2fpga\|fifo_pf acq_trigger_in\[10\] " "Info: Source node \"\|pc2fpga\|fifo_pf\" connects to port \"acq_trigger_in\[10\]\"" {  } { { "../Src/pc2fpga.v" "fifo_pf" { Text "D:/RedLogic/RCII_samples/USB_OUT/Src/pc2fpga.v" 15 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|pc2fpga\|fifo_pf acq_data_in\[10\] " "Info: Source node \"\|pc2fpga\|fifo_pf\" connects to port \"acq_data_in\[10\]\"" {  } { { "../Src/pc2fpga.v" "fifo_pf" { Text "D:/RedLogic/RCII_samples/USB_OUT/Src/pc2fpga.v" 15 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|pc2fpga\|fifo_rd acq_trigger_in\[11\] " "Info: Source node \"\|pc2fpga\|fifo_rd\" connects to port \"acq_trigger_in\[11\]\"" {  } { { "../Src/pc2fpga.v" "fifo_rd" { Text "D:/RedLogic/RCII_samples/USB_OUT/Src/pc2fpga.v" 19 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|pc2fpga\|fifo_rd acq_data_in\[11\] " "Info: Source node \"\|pc2fpga\|fifo_rd\" connects to port \"acq_data_in\[11\]\"" {  } { { "../Src/pc2fpga.v" "fifo_rd" { Text "D:/RedLogic/RCII_samples/USB_OUT/Src/pc2fpga.v" 19 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|pc2fpga\|fifo_wr acq_trigger_in\[12\] " "Info: Source node \"\|pc2fpga\|fifo_wr\" connects to port \"acq_trigger_in\[12\]\"" {  } { { "../Src/pc2fpga.v" "fifo_wr" { Text "D:/RedLogic/RCII_samples/USB_OUT/Src/pc2fpga.v" 18 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|pc2fpga\|fifo_wr acq_data_in\[12\] " "Info: Source node \"\|pc2fpga\|fifo_wr\" connects to port \"acq_data_in\[12\]\"" {  } { { "../Src/pc2fpga.v" "fifo_wr" { Text "D:/RedLogic/RCII_samples/USB_OUT/Src/pc2fpga.v" 18 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|pc2fpga\|rst acq_trigger_in\[13\] " "Info: Source node \"\|pc2fpga\|rst\" connects to port \"acq_trigger_in\[13\]\"" {  } { { "../Src/pc2fpga.v" "rst" { Text "D:/RedLogic/RCII_samples/USB_OUT/Src/pc2fpga.v" 13 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|pc2fpga\|rst acq_data_in\[13\] " "Info: Source node \"\|pc2fpga\|rst\" connects to port \"acq_data_in\[13\]\"" {  } { { "../Src/pc2fpga.v" "rst" { Text "D:/RedLogic/RCII_samples/USB_OUT/Src/pc2fpga.v" 13 -1 0 } }  } 0}  } {  } 0}