pc2fpga.map.qmsg

this is a sample about usb out transmission

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jun 27 23:31:07 2005 " "Info: Processing started: Mon Jun 27 23:31:07 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off USB_OUT -c pc2fpga " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off USB_OUT -c pc2fpga" {  } {  } 0}
{ "Warning" "WVRFX_VERI_IGNORED_ANONYMOUS_PORT" "pc2fpga pc2fpga.v(11) " "Warning: Verilog Module Declaration warning at pc2fpga.v(11): ignored anonymous port(s) indicated by duplicate or dangling comma(s) in the port list for module \"pc2fpga\"" {  } { { "../Src/pc2fpga.v" "" { Text "D:/RedLogic/RCII_samples/USB_OUT/Src/pc2fpga.v" 11 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../Src/pc2fpga.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../Src/pc2fpga.v" { { "Info" "ISGN_ENTITY_NAME" "1 pc2fpga " "Info: Found entity 1: pc2fpga" {  } { { "../Src/pc2fpga.v" "" { Text "D:/RedLogic/RCII_samples/USB_OUT/Src/pc2fpga.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "pc2fpga " "Info: Elaborating entity \"pc2fpga\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 pc2fpga.v(43) " "Warning: Verilog HDL assignment warning at pc2fpga.v(43): truncated value with size 32 to match size of target (1)" {  } { { "../Src/pc2fpga.v" "" { Text "D:/RedLogic/RCII_samples/USB_OUT/Src/pc2fpga.v" 43 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "fifo_empty pc2fpga.v(55) " "Warning: Verilog HDL Always Construct warning at pc2fpga.v(55): variable \"fifo_empty\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "../Src/pc2fpga.v" "" { Text "D:/RedLogic/RCII_samples/USB_OUT/Src/pc2fpga.v" 55 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 pc2fpga.v(81) " "Warning: Verilog HDL assignment warning at pc2fpga.v(81): truncated value with size 32 to match size of target (1)" {  } { { "../Src/pc2fpga.v" "" { Text "D:/RedLogic/RCII_samples/USB_OUT/Src/pc2fpga.v" 81 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 pc2fpga.v(82) " "Warning: Verilog HDL assignment warning at pc2fpga.v(82): truncated value with size 32 to match size of target (1)" {  } { { "../Src/pc2fpga.v" "" { Text "D:/RedLogic/RCII_samples/USB_OUT/Src/pc2fpga.v" 82 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd 3 1 " "Info: Found 3 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_signaltap_pack " "Info: Found design unit 1: sld_signaltap_pack" {  } { { "sld_signaltap.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 62 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 sld_signaltap-rtl " "Info: Found design unit 2: sld_signaltap-rtl" {  } { { "sld_signaltap.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 170 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_signaltap " "Info: Found entity 1: sld_signaltap" {  } { { "sld_signaltap.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 85 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd 14 7 " "Info: Found 14 design units, including 7 entities, in source file c:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_ela_control-rtl " "Info: Found design unit 1: sld_ela_control-rtl" {  } { { "sld_ela_control.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 118 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 sld_ela_level_seq_mgr-rtl " "Info: Found design unit 2: sld_ela_level_seq_mgr-rtl" {  } { { "sld_ela_control.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 844 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 sld_ela_state_machine-rtl " "Info: Found design unit 3: sld_ela_state_machine-rtl" {  } { { "sld_ela_control.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 1022 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "4 sld_ela_seg_state_machine-rtl " "Info: Found design unit 4: sld_ela_seg_state_machine-rtl" {  } { { "sld_ela_control.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 1125 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "5 sld_ela_post_trigger_counter-rtl " "Info: Found design unit 5: sld_ela_post_trigger_counter-rtl" {  } { { "sld_ela_control.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 1215 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "6 sld_ela_segment_mgr-rtl " "Info: Found design unit 6: sld_ela_segment_mgr-rtl" {  } { { "sld_ela_control.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 1342 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "7 sld_ela_basic_multi_level_trigger-rtl " "Info: Found design unit 7: sld_ela_basic_multi_level_trigger-rtl" {  } { { "sld_ela_control.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 1521 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_ela_control " "Info: Found entity 1: sld_ela_control" {  } { { "sld_ela_control.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 67 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "2 sld_ela_level_seq_mgr " "Info: Found entity 2: sld_ela_level_seq_mgr" {  } { { "sld_ela_control.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 817 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "3 sld_ela_state_machine " "Info: Found entity 3: sld_ela_state_machine" {  } { { "sld_ela_control.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 1000 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "4 sld_ela_seg_state_machine " "Info: Found entity 4: sld_ela_seg_state_machine" {  } { { "sld_ela_control.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 1105 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "5 sld_ela_post_trigger_counter " "Info: Found entity 5: sld_ela_post_trigger_counter" {  } { { "sld_ela_control.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 1195 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "6 sld_ela_segment_mgr " "Info: Found entity 6: sld_ela_segment_mgr" {  } { { "sld_ela_control.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 1319 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "7 sld_ela_basic_multi_level_trigger " "Info: Found entity 7: sld_ela_basic_multi_level_trigger" {  } { { "sld_ela_control.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 1487 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/lpm_shiftreg.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/lpm_shiftreg.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_shiftreg " "Info: Found entity 1: lpm_shiftreg" {  } { { "lpm_shiftreg.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_shiftreg.tdf" 37 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/sld_mbpmg.vhd 4 2 " "Info: Found 4 design units, including 2 entities, in source file c:/altera/quartus50/libraries/megafunctions/sld_mbpmg.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_mbpmg-rtl " "Info: Found design unit 1: sld_mbpmg-rtl" {  } { { "sld_mbpmg.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_mbpmg.vhd" 65 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 sld_sbpmg-rtl " "Info: Found design unit 2: sld_sbpmg-rtl" {  } { { "sld_mbpmg.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_mbpmg.vhd" 293 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_mbpmg " "Info: Found entity 1: sld_mbpmg" {  } { { "sld_mbpmg.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_mbpmg.vhd" 44 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "2 sld_sbpmg " "Info: Found entity 2: sld_sbpmg" {  } { { "sld_mbpmg.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_mbpmg.vhd" 272 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 227 1 0 } }  } 0}  } {  } 0}