pc2fpga.hif

this is a sample about usb out transmission

db|pc2fpga.(25).cnf
db|pc2fpga.(25).cnf
# user_parameter {
lpm_width
1
PARAMETER_UNKNOWN
USR
ONE_INPUT_CONSTANT
1
PARAMETER_UNKNOWN
USR
MODE
0
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CASCADE_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
CASCADE_CHAIN_LENGTH
2
CASCADE_CHAIN_LENGTH
USR
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
dataa0
datab0
aeb
}
# include_file {
c:|altera|quartus50|libraries|megafunctions|aglobal50.inc
1114066420
c:|altera|quartus50|libraries|megafunctions|comptree.inc
1107627994
}
# end
# entity
comptree
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|comptree.tdf
1114066448
6
# storage
db|pc2fpga.(26).cnf
db|pc2fpga.(26).cnf
# user_parameter {
lpm_width
2
PARAMETER_UNKNOWN
USR
CHAIN_LENGTH
1
PARAMETER_UNKNOWN
USR
ONE_INPUT_CONSTANT
1
PARAMETER_UNKNOWN
USR
OUTPUTS_CLOCKED
1
PARAMETER_UNKNOWN
USR
BURRIED_CLOCKED
0
PARAMETER_UNKNOWN
USR
MODE
0
PARAMETER_UNKNOWN
USR
}
# used_port {
dataa0
dataa1
datab0
datab1
aeb
}
# include_file {
c:|altera|quartus50|libraries|megafunctions|lpm_constant.inc
1107628524
c:|altera|quartus50|libraries|megafunctions|comptree.inc
1107627994
c:|altera|quartus50|libraries|megafunctions|cmpchain.inc
1107627964
}
# end
# entity
cmpchain
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|cmpchain.tdf
1114066448
6
# storage
db|pc2fpga.(27).cnf
db|pc2fpga.(27).cnf
# user_parameter {
lpm_width
2
PARAMETER_UNKNOWN
USR
ONE_INPUT_CONSTANT
1
PARAMETER_UNKNOWN
USR
MODE
0
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CASCADE_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
CASCADE_CHAIN_LENGTH
2
CASCADE_CHAIN_LENGTH
USR
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
dataa0
dataa1
datab0
datab1
aeb
}
# include_file {
c:|altera|quartus50|libraries|megafunctions|aglobal50.inc
1114066420
c:|altera|quartus50|libraries|megafunctions|comptree.inc
1107627994
}
# end
# entity
altshift
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|altshift.tdf
1114066454
6
# storage
db|pc2fpga.(28).cnf
db|pc2fpga.(28).cnf
# user_parameter {
WIDTH
1
PARAMETER_UNKNOWN
USR
DEPTH
0
PARAMETER_UNKNOWN
USR
}
# used_port {
data0
result0
}
# end
# entity
sld_acquisition_buffer
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|sld_acquisition_buffer.vhd
1114066240
4
# storage
db|pc2fpga.(29).cnf
db|pc2fpga.(29).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
ip_major_version
3
PARAMETER_DEC
USR
ip_minor_version
2
PARAMETER_DEC
USR
common_ip_version
0
PARAMETER_DEC
USR
data_bits
14
PARAMETER_DEC
USR
buffer_depth
1024
PARAMETER_DEC
USR
mem_address_bits
10
PARAMETER_DEC
USR
ela_status_bits
3
PARAMETER_DEC
USR
}
# end
# entity
lpm_counter
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|lpm_counter.tdf
1114066448
6
# storage
db|pc2fpga.(30).cnf
db|pc2fpga.(30).cnf
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
10
PARAMETER_DEC
USR
LPM_DIRECTION
UP
PARAMETER_UNKNOWN
USR
LPM_MODULUS
1024
PARAMETER_DEC
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
NOT_GATE_PUSH_BACK
ON
NOT_GATE_PUSH_BACK
USR
CARRY_CNT_EN
OFF
PARAMETER_UNKNOWN
USR
LABWIDE_SCLR
ON
PARAMETER_UNKNOWN
DEF
USE_NEW_VERSION
TRUE
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
cntr_nt9
PARAMETER_UNKNOWN
USR
}
# used_port {
aclr
clk_en
clock
cout
q0
q1
q2
q3
q4
q5
q6
q7
q8
q9
}
# include_file {
c:|altera|quartus50|libraries|megafunctions|lpm_constant.inc
1107628524
c:|altera|quartus50|libraries|megafunctions|dffeea.inc
1107628164
c:|altera|quartus50|libraries|megafunctions|aglobal50.inc
1114066420
c:|altera|quartus50|libraries|megafunctions|lpm_decode.inc
1107628570
c:|altera|quartus50|libraries|megafunctions|lpm_add_sub.inc
1107628408
c:|altera|quartus50|libraries|megafunctions|cmpconst.inc
1107627980
c:|altera|quartus50|libraries|megafunctions|lpm_compare.inc
1107628500
c:|altera|quartus50|libraries|megafunctions|lpm_counter.inc
1107628548
c:|altera|quartus50|libraries|megafunctions|alt_synch_counter.inc
1107626664
c:|altera|quartus50|libraries|megafunctions|alt_synch_counter_f.inc
1107626680
c:|altera|quartus50|libraries|megafunctions|alt_counter_f10ke.inc
1107626320
c:|altera|quartus50|libraries|megafunctions|alt_counter_stratix.inc
1107626334
}
# end
# entity
cntr_nt9
# case_insensitive
# source_file
db|cntr_nt9.tdf
1119886276
6
# storage
db|pc2fpga.(31).cnf
db|pc2fpga.(31).cnf
# used_port {
clock
clk_en
aclr
q0
q1
q2
q3
q4
q5
q6
q7
q8
q9
cout
}
# end
# entity
lpm_ff
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|lpm_ff.tdf
1114066452
6
# storage
db|pc2fpga.(32).cnf
db|pc2fpga.(32).cnf
# user_parameter {
LPM_WIDTH
10
PARAMETER_DEC
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_FFTYPE
DFF
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
NOTHING
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
aclr
clock
data0
data1
data2
data3
data4
data5
data6
data7
data8
data9
enable
q0
q1
q2
q3
q4
q5
q6
q7
q8
q9
}
# include_file {
c:|altera|quartus50|libraries|megafunctions|lpm_constant.inc
1107628524
c:|altera|quartus50|libraries|megafunctions|aglobal50.inc
1114066420
}
# end
# entity
altsyncram
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|altsyncram.tdf
1114066438
6
# storage
db|pc2fpga.(33).cnf
db|pc2fpga.(33).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
14
PARAMETER_DEC
USR
WIDTHAD_A
10
PARAMETER_DEC
USR
NUMWORDS_A
1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WIDTH_B
14
PARAMETER_DEC
USR
WIDTHAD_B
10
PARAMETER_DEC
USR
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_DEC
USR
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_DEC
USR
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
INIT_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
USR
MAXIMUM_DEPTH
0
PARAMETER_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_th92
PARAMETER_UNKNOWN
USR
}
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
address_a8
address_a9
address_b0
address_b1
address_b2
address_b3
address_b4
address_b5
address_b6
address_b7
address_b8
address_b9
clock0
clock1
clocken1
data_a0
data_a10
data_a11
data_a12
data_a13
data_a1
data_a2
data_a3
data_a4
data_a5
data_a6
data_a7
data_a8
data_a9
q_b0
q_b10
q_b11
q_b12
q_b13
q_b1
q_b2
q_b3
q_b4
q_b5
q_b6
q_b7
q_b8
q_b9
wren_a
}
# include_file {
c:|altera|quartus50|libraries|megafunctions|aglobal50.inc
1114066420
c:|altera|quartus50|libraries|megafunctions|lpm_decode.inc
1107628570
c:|altera|quartus50|libraries|megafunctions|stratix_ram_block.inc
1107629592
c:|altera|quartus50|libraries|megafunctions|lpm_mux.inc
1107628776
c:|altera|quartus50|libraries|megafunctions|altsyncram.inc
1107627506
c:|altera|quartus50|libraries|megafunctions|a_rdenreg.inc
1107626148
c:|altera|quartus50|libraries|megafunctions|altrom.inc
1107627422
c:|altera|quartus50|libraries|megafunctions|altram.inc
1107627384
c:|altera|quartus50|libraries|megafunctions|altdpram.inc
1107627082
c:|altera|quartus50|libraries|megafunctions|altqpram.inc
1107627362
}
# end
# entity
altsyncram_th92
# case_insensitive
# source_file
db|altsyncram_th92.tdf
1119886278
6
# storage
db|pc2fpga.(34).cnf
db|pc2fpga.(34).cnf
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
data_a0
data_a1
data_a2
data_a3
data_a4
data_a5
data_a6
data_a7
data_a8
data_a9
data_a10
data_a11
data_a12
data_a13
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
address_a8
address_a9
address_b0
address_b1
address_b2
address_b3
address_b4
address_b5
address_b6
address_b7
address_b8
address_b9
clock0
clock1
clocken1
q_b0
q_b1
q_b2
q_b3
q_b4
q_b5
q_b6
q_b7
q_b8
q_b9
q_b10
q_b11
q_b12
q_b13
}
# memory_file {
none
0
}
# end
# entity
sld_offload_buffer_mgr
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|sld_acquisition_buffer.vhd
1114066240
4
# storage
db|pc2fpga.(35).cnf
db|pc2fpga.(35).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
ip_major_version
3
PARAMETER_DEC
USR
ip_minor_version
2
PARAMETER_DEC
USR
common_ip_version
0
PARAMETER_DEC
USR
buffer_depth
1024
PARAMETER_DEC
USR
mem_address_bits
10
PARAMETER_DEC
USR
data_bits
14