pc2fpga.tan.qmsg

this is a sample about usb out transmission

{ "Info" "ITDB_FULL_TCO_RESULT" "clk fifo_rd fifo_rd~reg0 17.681 ns register " "Info: tco from clock \"clk\" to destination pin \"fifo_rd\" through register \"fifo_rd~reg0\" is 17.681 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 10.645 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 10.645 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 1; CLK Node = 'clk'" {  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "" { clk } "NODE_NAME" } "" } } { "../Src/pc2fpga.v" "" { Text "D:/RedLogic/RCII_samples/USB_OUT/Src/pc2fpga.v" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.015 ns) + CELL(0.935 ns) 6.419 ns clkin 2 REG LC_X8_Y13_N5 176 " "Info: 2: + IC(4.015 ns) + CELL(0.935 ns) = 6.419 ns; Loc. = LC_X8_Y13_N5; Fanout = 176; REG Node = 'clkin'" {  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "4.950 ns" { clk clkin } "NODE_NAME" } "" } } { "../Src/pc2fpga.v" "" { Text "D:/RedLogic/RCII_samples/USB_OUT/Src/pc2fpga.v" 31 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.515 ns) + CELL(0.711 ns) 10.645 ns fifo_rd~reg0 3 REG LC_X29_Y8_N0 4 " "Info: 3: + IC(3.515 ns) + CELL(0.711 ns) = 10.645 ns; Loc. = LC_X29_Y8_N0; Fanout = 4; REG Node = 'fifo_rd~reg0'" {  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "4.226 ns" { clkin fifo_rd~reg0 } "NODE_NAME" } "" } } { "../Src/pc2fpga.v" "" { Text "D:/RedLogic/RCII_samples/USB_OUT/Src/pc2fpga.v" 73 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns 29.26 % " "Info: Total cell delay = 3.115 ns ( 29.26 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.530 ns 70.74 % " "Info: Total interconnect delay = 7.530 ns ( 70.74 % )" {  } {  } 0}  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "10.645 ns" { clk clkin fifo_rd~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "10.645 ns" { clk clk~out0 clkin fifo_rd~reg0 } { 0.000ns 0.000ns 4.015ns 3.515ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "../Src/pc2fpga.v" "" { Text "D:/RedLogic/RCII_samples/USB_OUT/Src/pc2fpga.v" 73 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.812 ns + Longest register pin " "Info: + Longest register to pin delay is 6.812 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fifo_rd~reg0 1 REG LC_X29_Y8_N0 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X29_Y8_N0; Fanout = 4; REG Node = 'fifo_rd~reg0'" {  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "" { fifo_rd~reg0 } "NODE_NAME" } "" } } { "../Src/pc2fpga.v" "" { Text "D:/RedLogic/RCII_samples/USB_OUT/Src/pc2fpga.v" 73 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.688 ns) + CELL(2.124 ns) 6.812 ns fifo_rd 2 PIN PIN_57 0 " "Info: 2: + IC(4.688 ns) + CELL(2.124 ns) = 6.812 ns; Loc. = PIN_57; Fanout = 0; PIN Node = 'fifo_rd'" {  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "6.812 ns" { fifo_rd~reg0 fifo_rd } "NODE_NAME" } "" } } { "../Src/pc2fpga.v" "" { Text "D:/RedLogic/RCII_samples/USB_OUT/Src/pc2fpga.v" 19 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns 31.18 % " "Info: Total cell delay = 2.124 ns ( 31.18 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.688 ns 68.82 % " "Info: Total interconnect delay = 4.688 ns ( 68.82 % )" {  } {  } 0}  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "6.812 ns" { fifo_rd~reg0 fifo_rd } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.812 ns" { fifo_rd~reg0 fifo_rd } { 0.000ns 4.688ns } { 0.000ns 2.124ns } } }  } 0}  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "10.645 ns" { clk clkin fifo_rd~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "10.645 ns" { clk clk~out0 clkin fifo_rd~reg0 } { 0.000ns 0.000ns 4.015ns 3.515ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "6.812 ns" { fifo_rd~reg0 fifo_rd } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.812 ns" { fifo_rd~reg0 fifo_rd } { 0.000ns 4.688ns } { 0.000ns 2.124ns } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "altera_internal_jtag~TDO altera_reserved_tdo 2.124 ns Longest " "Info: Longest tpd from source pin \"altera_internal_jtag~TDO\" to destination pin \"altera_reserved_tdo\" is 2.124 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TDO 1 PIN JTAG_X1_Y13_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y13_N1; Fanout = 1; PIN Node = 'altera_internal_jtag~TDO'" {  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCI