pc2fpga.tan.qmsg

this is a sample about usb out transmission

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[4\] register sld_hub:sld_hub_inst\|hub_tdo 89.64 MHz 11.156 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 89.64 MHz between source register \"sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[4\]\" and destination register \"sld_hub:sld_hub_inst\|hub_tdo\" (period= 11.156 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.317 ns + Longest register register " "Info: + Longest register to register delay is 5.317 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[4\] 1 REG LC_X36_Y9_N1 44 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X36_Y9_N1; Fanout = 44; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[4\]'" {  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] } "NODE_NAME" } "" } } { "sld_dffex.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.151 ns) + CELL(0.590 ns) 2.741 ns sld_hub:sld_hub_inst\|hub_tdo~279 2 COMB LC_X36_Y11_N6 1 " "Info: 2: + IC(2.151 ns) + CELL(0.590 ns) = 2.741 ns; Loc. = LC_X36_Y11_N6; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~279'" {  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "2.741 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] sld_hub:sld_hub_inst|hub_tdo~279 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.532 ns) + CELL(0.114 ns) 4.387 ns sld_hub:sld_hub_inst\|hub_tdo~280 3 COMB LC_X37_Y9_N8 1 " "Info: 3: + IC(1.532 ns) + CELL(0.114 ns) = 4.387 ns; Loc. = LC_X37_Y9_N8; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~280'" {  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "1.646 ns" { sld_hub:sld_hub_inst|hub_tdo~279 sld_hub:sld_hub_inst|hub_tdo~280 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.452 ns) + CELL(0.478 ns) 5.317 ns sld_hub:sld_hub_inst\|hub_tdo 4 REG LC_X37_Y9_N5 0 " "Info: 4: + IC(0.452 ns) + CELL(0.478 ns) = 5.317 ns; Loc. = LC_X37_Y9_N5; Fanout = 0; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "0.930 ns" { sld_hub:sld_hub_inst|hub_tdo~280 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.182 ns 22.23 % " "Info: Total cell delay = 1.182 ns ( 22.23 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.135 ns 77.77 % " "Info: Total interconnect delay = 4.135 ns ( 77.77 % )" {  } {  } 0}  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "5.317 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] sld_hub:sld_hub_inst|hub_tdo~279 sld_hub:sld_hub_inst|hub_tdo~280 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.317 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] sld_hub:sld_hub_inst|hub_tdo~279 sld_hub:sld_hub_inst|hub_tdo~280 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 2.151ns 1.532ns 0.452ns } { 0.000ns 0.590ns 0.114ns 0.478ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.283 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.283 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y13_N1 230 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y13_N1; Fanout = 230; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.572 ns) + CELL(0.711 ns) 5.283 ns sld_hub:sld_hub_inst\|hub_tdo 2 REG LC_X37_Y9_N5 0 " "Info: 2: + IC(4.572 ns) + CELL(0.711 ns) = 5.283 ns; Loc. = LC_X37_Y9_N5; Fanout = 0; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "5.283 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 13.46 % " "Info: Total cell delay = 0.711 ns ( 13.46 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.572 ns 86.54 % " "Info: Total interconnect delay = 4.572 ns ( 86.54 % )" {  } {  } 0}  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "5.283 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.283 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.572ns } { 0.000ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 5.283 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 5.283 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y13_N1 230 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y13_N1; Fanout = 230; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.572 ns) + CELL(0.711 ns) 5.283 ns sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[4\] 2 REG LC_X36_Y9_N1 44 " "Info: 2: + IC(4.572 ns) + CELL(0.711 ns) = 5.283 ns; Loc. = LC_X36_Y9_N1; Fanout = 44; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[4\]'" {  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "5.283 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] } "NODE_NAME" } "" } } { "sld_dffex.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 13.46 % " "Info: Total cell delay = 0.711 ns ( 13.46 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.572 ns 86.54 % " "Info: Total interconnect delay = 4.572 ns ( 86.54 % )" {  } {  } 0}  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "5.283 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.283 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] } { 0.000ns 4.572ns } { 0.000ns 0.711ns } } }  } 0}  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "5.283 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.283 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.572ns } { 0.000ns 0.711ns } } } { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "5.283 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.283 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] } { 0.000ns 4.572ns } { 0.000ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "sld_dffex.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "sld_dffex.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0}  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "5.317 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] sld_hub:sld_hub_inst|hub_tdo~279 sld_hub:sld_hub_inst|hub_tdo~280 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.317 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] sld_hub:sld_hub_inst|hub_tdo~279 sld_hub:sld_hub_inst|hub_tdo~280 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 2.151ns 1.532ns 0.452ns } { 0.000ns 0.590ns 0.114ns 0.478ns } } } { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "5.283 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.283 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.572ns } { 0.000ns 0.711ns } } } { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "5.283 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.283 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] } { 0.000ns 4.572ns } { 0.000ns 0.711ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA_0\|Q\[0\] altera_internal_jtag~TMSUTAP altera_internal_jtag~TCKUTAP 1.617 ns register " "Info: tsu for register \"sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA_0\|Q\[0\]\" (data pin = \"altera_internal_jtag~TMSUTAP\", clock pin = \"altera_internal_jtag~TCKUTAP\") is 1.617 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.863 ns + Longest pin register " "Info: + Longest pin to register delay is 6.863 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TMSUTAP 1 PIN JTAG_X1_Y13_N1 22 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y13_N1; Fanout = 22; PIN Node = 'altera_internal_jtag~TMSUTAP'" {  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "" { altera_internal_jtag~TMSUTAP } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.445 ns) + CELL(0.292 ns) 4.737 ns sld_hub:sld_hub_inst\|IRF_ENA_ENABLE~21 2 COMB LC_X38_Y9_N6 2 " "Info: 2: + IC(4.445 ns) + CELL(0.292 ns) = 4.737 ns; Loc. = LC_X38_Y9_N6; Fanout = 2; COMB Node = 'sld_hub:sld_hub_inst\|IRF_ENA_ENABLE~21'" {  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "4.737 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|IRF_ENA_ENABLE~21 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 371 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.259 ns) + CELL(0.867 ns) 6.863 ns sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA_0\|Q\[0\] 3 REG LC_X38_Y10_N4 3 " "Info: 3: + IC(1.259 ns) + CELL(0.867 ns) = 6.863 ns; Loc. = LC_X38_Y10_N4; Fanout = 3; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA_0\|Q\[0\]'" {  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "2.126 ns" { sld_hub:sld_hub_inst|IRF_ENA_ENABLE~21 sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] } "NODE_NAME" } "" } } { "sld_dffex.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.159 ns 16.89 % " "Info: Total cell delay = 1.159 ns ( 16.89 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.704 ns 83.11 % " "Info: Total interconnect delay = 5.704 ns ( 83.11 % )" {  } {  } 0}  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "6.863 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|IRF_ENA_ENABLE~21 sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.863 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|IRF_ENA_ENABLE~21 sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] } { 0.000ns 4.445ns 1.259ns } { 0.000ns 0.292ns 0.867ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "sld_dffex.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.283 ns - Shortest register " "Info: - Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.283 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y13_N1 230 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y13_N1; Fanout = 230; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.572 ns) + CELL(0.711 ns) 5.283 ns sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA_0\|Q\[0\] 2 REG LC_X38_Y10_N4 3 " "Info: 2: + IC(4.572 ns) + CELL(0.711 ns) = 5.283 ns; Loc. = LC_X38_Y10_N4; Fanout = 3; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA_0\|Q\[0\]'" {  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "5.283 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] } "NODE_NAME" } "" } } { "sld_dffex.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 13.46 % " "Info: Total cell delay = 0.711 ns ( 13.46 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.572 ns 86.54 % " "Info: Total interconnect delay = 4.572 ns ( 86.54 % )" {  } {  } 0}  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "5.283 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.283 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] } { 0.000ns 4.572ns } { 0.000ns 0.711ns } } }  } 0}  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "6.863 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|IRF_ENA_ENABLE~21 sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.863 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|IRF_ENA_ENABLE~21 sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] } { 0.000ns 4.445ns 1.259ns } { 0.000ns 0.292ns 0.867ns } } } { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "5.283 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.283 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] } { 0.000ns 4.572ns } { 0.000ns 0.711ns } } }  } 0}