pc2fpga.tan.qmsg

this is a sample about usb out transmission

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clkin " "Info: Detected ripple clock \"clkin\" as buffer" {  } { { "../Src/pc2fpga.v" "" { Text "D:/RedLogic/RCII_samples/USB_OUT/Src/pc2fpga.v" 31 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clkin" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_nt9:auto_generated\|safe_q\[1\] register sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_nt9:auto_generated\|safe_q\[5\] 139.59 MHz 7.164 ns Internal " "Info: Clock \"clk\" has Internal fmax of 139.59 MHz between source register \"sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_nt9:auto_generated\|safe_q\[1\]\" and destination register \"sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_nt9:auto_generated\|safe_q\[5\]\" (period= 7.164 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.903 ns + Longest register register " "Info: + Longest register to register delay is 6.903 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_nt9:auto_generated\|safe_q\[1\] 1 REG LC_X32_Y10_N6 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X32_Y10_N6; Fanout = 9; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_nt9:auto_generated\|safe_q\[1\]'" {  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "" { sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|safe_q[1] } "NODE_NAME" } "" } } { "db/cntr_nt9.tdf" "" { Text "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/cntr_nt9.tdf" 126 8 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.536 ns) + CELL(0.575 ns) 1.111 ns sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_nt9:auto_generated\|counter_cella1~COUTCOUT1_1 2 COMB LC_X32_Y10_N6 2 " "Info: 2: + IC(0.536 ns) + CELL(0.575 ns) = 1.111 ns; Loc. = LC_X32_Y10_N6; Fanout = 2; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_nt9:auto_generated\|counter_cella1~COUTCOUT1_1'" {  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "1.111 ns" { sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|safe_q[1] sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|counter_cella1~COUTCOUT1_1 } "NODE_NAME" } "" } } { "db/cntr_nt9.tdf" "" { Text "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/cntr_nt9.tdf" 41 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.191 ns sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_nt9:auto_generated\|counter_cella2~COUTCOUT1_1 3 COMB LC_X32_Y10_N7 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.191 ns; Loc. = LC_X32_Y10_N7; Fanout = 2; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_nt9:auto_generated\|counter_cella2~COUTCOUT1_1'" {  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "0.080 ns" { sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|counter_cella1~COUTCOUT1_1 sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|counter_cella2~COUTCOUT1_1 } "NODE_NAME" } "" } } { "db/cntr_nt9.tdf" "" { Text "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/cntr_nt9.tdf" 49 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.271 ns sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_nt9:auto_generated\|counter_cella3~COUTCOUT1_1 4 COMB LC_X32_Y10_N8 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.271 ns; Loc. = LC_X32_Y10_N8; Fanout = 2; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_nt9:auto_generated\|counter_cella3~COUTCOUT1_1'" {  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "0.080 ns" { sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|counter_cella2~COUTCOUT1_1 sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|counter_cella3~COUTCOUT1_1 } "NODE_NAME" } "" } } { "db/cntr_nt9.tdf" "" { Text "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/cntr_nt9.tdf" 57 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 1.529 ns sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_nt9:auto_generated\|counter_cella4~COUT 5 COMB LC_X32_Y10_N9 6 " "Info: 5: + IC(0.000 ns) + CELL(0.258 ns) = 1.529 ns; Loc. = LC_X32_Y10_N9; Fanout = 6; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_nt9:auto_generated\|counter_cella4~COUT'" {  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "0.258 ns" { sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|counter_cella3~COUTCOUT1_1 sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|counter_cella4~COUT } "NODE_NAME" } "" } } { "db/cntr_nt9.tdf" "" { Text "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/cntr_nt9.tdf" 65 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 1.665 ns sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_nt9:auto_generated\|counter_cella9~COUT 6 COMB LC_X32_Y9_N4 1 " "Info: 6: + IC(0.000 ns) + CELL(0.136 ns) = 1.665 ns; Loc. = LC_X32_Y9_N4; Fanout = 1; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_nt9:auto_generated\|counter_cella9~COUT'" {  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "0.136 ns" { sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|counter_cella4~COUT sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|counter_cella9~COUT } "NODE_NAME" } "" } } { "db/cntr_nt9.tdf" "" { Text "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/cntr_nt9.tdf" 105 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.621 ns) 2.286 ns sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_nt9:auto_generated\|cout 7 COMB LC_X32_Y9_N5 4 " "Info: 7: + IC(0.000 ns) + CELL(0.621 ns) = 2.286 ns; Loc. = LC_X32_Y9_N5; Fanout = 4; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_nt9:auto_generated\|cout'" {  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "0.621 ns" { sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|counter_cella9~COUT sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|cout } "NODE_NAME" } "" } } { "db/cntr_nt9.tdf" "" { Text "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/cntr_nt9.tdf" 158 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.204 ns) + CELL(0.442 ns) 3.932 ns sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|is_buffer_wrapped~0 8 COMB LC_X32_Y10_N0 1 " "Info: 8: + IC(1.204 ns) + CELL(0.442 ns) = 3.932 ns; Loc. = LC_X32_Y10_N0; Fanout = 1; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|is_buffer_wrapped~0'" {  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "1.646 ns" { sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|cout sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|is_buffer_wrapped~0 } "NODE_NAME" } "" } } { "sld_acquisition_buffer.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_acquisition_buffer.vhd" 69 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.419 ns) + CELL(0.442 ns) 4.793 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|buffer_write_addr_adv_ena_int~53 9 COMB LC_X32_Y10_N4 10 " "Info: 9: + IC(0.419 ns) + CELL(0.442 ns) = 4.793 ns; Loc. = LC_X32_Y10_N4; Fanout = 10; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|buffer_write_addr_adv_ena_int~53'" {  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "0.861 ns" { sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|is_buffer_wrapped~0 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|buffer_write_addr_adv_ena_int~53 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.243 ns) + CELL(0.867 ns) 6.903 ns sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_nt9:auto_generated\|safe_q\[5\] 10 REG LC_X32_Y9_N0 9 " "Info: 10: + IC(1.243 ns) + CELL(0.867 ns) = 6.903 ns; Loc. = LC_X32_Y9_N0; Fanout = 9; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_nt9:auto_generated\|safe_q\[5\]'" {  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "2.110 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|buffer_write_addr_adv_ena_int~53 sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|safe_q[5] } "NODE_NAME" } "" } } { "db/cntr_nt9.tdf" "" { Text "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/cntr_nt9.tdf" 126 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.501 ns 50.72 % " "Info: Total cell delay = 3.501 ns ( 50.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.402 ns 49.28 % " "Info: Total interconnect delay = 3.402 ns ( 49.28 % )" {  } {  } 0}  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "6.903 ns" { sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|safe_q[1] sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|counter_cella1~COUTCOUT1_1 sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|counter_cella2~COUTCOUT1_1 sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|counter_cella3~COUTCOUT1_1 sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|counter_cella4~COUT sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|counter_cella9~COUT sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|cout sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|is_buffer_wrapped~0 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|buffer_write_addr_adv_ena_int~53 sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|safe_q[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.903 ns" { sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|safe_q[1] sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|counter_cella1~COUTCOUT1_1 sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|counter_cella2~COUTCOUT1_1 sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|counter_cella3~COUTCOUT1_1 sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|counter_cella4~COUT sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|counter_cella9~COUT sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|cout sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|is_buffer_wrapped~0 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|buffer_write_addr_adv_ena_int~53 sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|safe_q[5] } { 0.000ns 0.536ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.204ns 0.419ns 1.243ns } { 0.000ns 0.575ns 0.080ns 0.080ns 0.258ns 0.136ns 0.621ns 0.442ns 0.442ns 0.867ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 10.645 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 10.645 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 1; CLK Node = 'clk'" {  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "" { clk } "NODE_NAME" } "" } } { "../Src/pc2fpga.v" "" { Text "D:/RedLogic/RCII_samples/USB_OUT/Src/pc2fpga.v" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.015 ns) + CELL(0.935 ns) 6.419 ns clkin 2 REG LC_X8_Y13_N5 176 " "Info: 2: + IC(4.015 ns) + CELL(0.935 ns) = 6.419 ns; Loc. = LC_X8_Y13_N5; Fanout = 176; REG Node = 'clkin'" {  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "4.950 ns" { clk clkin } "NODE_NAME" } "" } } { "../Src/pc2fpga.v" "" { Text "D:/RedLogic/RCII_samples/USB_OUT/Src/pc2fpga.v" 31 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.515 ns) + CELL(0.711 ns) 10.645 ns sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_nt9:auto_generated\|safe_q\[5\] 3 REG LC_X32_Y9_N0 9 " "Info: 3: + IC(3.515 ns) + CELL(0.711 ns) = 10.645 ns; Loc. = LC_X32_Y9_N0; Fanout = 9; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_nt9:auto_generated\|safe_q\[5\]'" {  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "4.226 ns" { clkin sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|safe_q[5] } "NODE_NAME" } "" } } { "db/cntr_nt9.tdf" "" { Text "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/cntr_nt9.tdf" 126 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns 29.26 % " "Info: Total cell delay = 3.115 ns ( 29.26 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.530 ns 70.74 % " "Info: Total interconnect delay = 7.530 ns ( 70.74 % )" {  } {  } 0}  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "10.645 ns" { clk clkin sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|safe_q[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "10.645 ns" { clk clk~out0 clkin sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|safe_q[5] } { 0.000ns 0.000ns 4.015ns 3.515ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 10.645 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 10.645 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 1; CLK Node = 'clk'" {  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "" { clk } "NODE_NAME" } "" } } { "../Src/pc2fpga.v" "" { Text "D:/RedLogic/RCII_samples/USB_OUT/Src/pc2fpga.v" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.015 ns) + CELL(0.935 ns) 6.419 ns clkin 2 REG LC_X8_Y13_N5 176 " "Info: 2: + IC(4.015 ns) + CELL(0.935 ns) = 6.419 ns; Loc. = LC_X8_Y13_N5; Fanout = 176; REG Node = 'clkin'" {  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "4.950 ns" { clk clkin } "NODE_NAME" } "" } } { "../Src/pc2fpga.v" "" { Text "D:/RedLogic/RCII_samples/USB_OUT/Src/pc2fpga.v" 31 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.515 ns) + CELL(0.711 ns) 10.645 ns sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_nt9:auto_generated\|safe_q\[1\] 3 REG LC_X32_Y10_N6 9 " "Info: 3: + IC(3.515 ns) + CELL(0.711 ns) = 10.645 ns; Loc. = LC_X32_Y10_N6; Fanout = 9; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_nt9:auto_generated\|safe_q\[1\]'" {  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "4.226 ns" { clkin sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|safe_q[1] } "NODE_NAME" } "" } } { "db/cntr_nt9.tdf" "" { Text "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/cntr_nt9.tdf" 126 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns 29.26 % " "Info: Total cell delay = 3.115 ns ( 29.26 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.530 ns 70.74 % " "Info: Total interconnect delay = 7.530 ns ( 70.74 % )" {  } {  } 0}  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "10.645 ns" { clk clkin sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|safe_q[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "10.645 ns" { clk clk~out0 clkin sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|safe_q[1] } { 0.000ns 0.000ns 4.015ns 3.515ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0}  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "10.645 ns" { clk clkin sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|safe_q[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "10.645 ns" { clk clk~out0 clkin sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|safe_q[5] } { 0.000ns 0.000ns 4.015ns 3.515ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "10.645 ns" { clk clkin sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|safe_q[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "10.645 ns" { clk clk~out0 clkin sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|safe_q[1] } { 0.000ns 0.000ns 4.015ns 3.515ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "db/cntr_nt9.tdf" "" { Text "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/cntr_nt9.tdf" 126 8 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "db/cntr_nt9.tdf" "" { Text "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/cntr_nt9.tdf" 126 8 0 } }  } 0}  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "6.903 ns" { sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|safe_q[1] sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|counter_cella1~COUTCOUT1_1 sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|counter_cella2~COUTCOUT1_1 sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|counter_cella3~COUTCOUT1_1 sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|counter_cella4~COUT sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|counter_cella9~COUT sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|cout sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|is_buffer_wrapped~0 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|buffer_write_addr_adv_ena_int~53 sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|safe_q[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.903 ns" { sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|safe_q[1] sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|counter_cella1~COUTCOUT1_1 sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|counter_cella2~COUTCOUT1_1 sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|counter_cella3~COUTCOUT1_1 sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|counter_cella4~COUT sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|counter_cella9~COUT sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|cout sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|is_buffer_wrapped~0 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|buffer_write_addr_adv_ena_int~53 sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|safe_q[5] } { 0.000ns 0.536ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.204ns 0.419ns 1.243ns } { 0.000ns 0.575ns 0.080ns 0.080ns 0.258ns 0.136ns 0.621ns 0.442ns 0.442ns 0.867ns } } } { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "10.645 ns" { clk clkin sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|safe_q[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "10.645 ns" { clk clk~out0 clkin sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|safe_q[5] } { 0.000ns 0.000ns 4.015ns 3.515ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "10.645 ns" { clk clkin sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|safe_q[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "10.645 ns" { clk clk~out0 clkin sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|safe_q[1] } { 0.000ns 0.000ns 4.015ns 3.515ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0}