pc2fpga.fit.qmsg

this is a sample about usb out transmission

{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.749 ns register register " "Info: Estimated most critical path is register to register delay of 3.749 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[4\] 1 REG LAB_X36_Y9 144 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X36_Y9; Fanout = 144; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[4\]'" {  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] } "NODE_NAME" } "" } } { "sld_dffex.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.924 ns) + CELL(0.590 ns) 1.514 ns sld_hub:sld_hub_inst\|hub_tdo~279 2 COMB LAB_X36_Y11 1 " "Info: 2: + IC(0.924 ns) + CELL(0.590 ns) = 1.514 ns; Loc. = LAB_X36_Y11; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~279'" {  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "1.514 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] sld_hub:sld_hub_inst|hub_tdo~279 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.093 ns) + CELL(0.292 ns) 2.899 ns sld_hub:sld_hub_inst\|hub_tdo~280 3 COMB LAB_X37_Y9 1 " "Info: 3: + IC(1.093 ns) + CELL(0.292 ns) = 2.899 ns; Loc. = LAB_X37_Y9; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~280'" {  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "1.385 ns" { sld_hub:sld_hub_inst|hub_tdo~279 sld_hub:sld_hub_inst|hub_tdo~280 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.372 ns) + CELL(0.478 ns) 3.749 ns sld_hub:sld_hub_inst\|hub_tdo 4 REG LAB_X37_Y9 0 " "Info: 4: + IC(0.372 ns) + CELL(0.478 ns) = 3.749 ns; Loc. = LAB_X37_Y9; Fanout = 0; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "0.850 ns" { sld_hub:sld_hub_inst|hub_tdo~280 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.360 ns 36.28 % " "Info: Total cell delay = 1.360 ns ( 36.28 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.389 ns 63.72 % " "Info: Total interconnect delay = 2.389 ns ( 63.72 % )" {  } {  } 0}  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "3.749 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] sld_hub:sld_hub_inst|hub_tdo~279 sld_hub:sld_hub_inst|hub_tdo~280 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Info: Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "1 5 " "Info: Average interconnect usage is 1% of the available device resources. Peak interconnect usage is 5%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:02 " "Info: Fitter routing operations ending: elapsed time is 00:00:02" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements" {  } {  } 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "sld_hub:sld_hub_inst\|sld_dffex:RESET\|Q\[0\] " "Info: Node sld_hub:sld_hub_inst\|sld_dffex:RESET\|Q\[0\] uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|sld_dffex:BROADCAST\|Q\[0\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|sld_dffex:BROADCAST\|Q\[0\] -- routed using non-global resources" {  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "" { sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:BROADCAST\|Q\[0\]" } } } } { "sld_dffex.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "D:/RedLogic/RCII_samples/USB_OUT/Proj/pc2fpga.fld" "" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/pc2fpga.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] } "NODE_NAME" } }  } 0}  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "" { sld_hub:sld_hub_inst|sld_dffex:RESET|Q[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:RESET\|Q\[0\]" } } } } { "sld_dffex.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "D:/RedLogic/RCII_samples/USB_OUT/Proj/pc2fpga.fld" "" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/pc2fpga.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:RESET|Q[0] } "NODE_NAME" } }  } 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\] " "Info: Node sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\] uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|jtag_debug_mode_usr1 " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|jtag_debug_mode_usr1 -- routed using non-global resources" {  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|jtag_debug_mode_usr1" } } } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 381 -1 0 } } { "D:/RedLogic/RCII_samples/USB_OUT/Proj/pc2fpga.fld" "" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/pc2fpga.fld" "" "" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|jtag_debug_mode_usr0 " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|jtag_debug_mode_usr0 -- routed using non-global resources" {  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "" { sld_hub:sld_hub_inst|jtag_debug_mode_usr0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|jtag_debug_mode_usr0" } } } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 380 -1 0 } } { "D:/RedLogic/RCII_samples/USB_OUT/Proj/pc2fpga.fld" "" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/pc2fpga.fld" "" "" { sld_hub:sld_hub_inst|jtag_debug_mode_usr0 } "NODE_NAME" } }  } 0}  } { { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\]" } } } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 1014 -1 0 } } { "D:/RedLogic/RCII_samples/USB_OUT/Proj/pc2fpga.fld" "" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/pc2fpga.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0] } "NODE_NAME" } }  } 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "1 " "Warning: The following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "fifo_wr VCC " "Info: Pin fifo_wr has VCC driving its datain port" {  } { { "../Src/pc2fpga.v" "" { Text "D:/RedLogic/RCII_samples/USB_OUT/Src/pc2fpga.v" 18 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "fifo_wr" } } } } { "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/" "" "" { fifo_wr } "NODE_NAME" } "" } } { "D:/RedLogic/RCII_samples/USB_OUT/Proj/pc2fpga.fld" "" { Floorplan "D:/RedLogic/RCII_samples/USB_OUT/Proj/pc2fpga.fld" "" "" { fifo_wr } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Jun 27 23:31:51 2005 " "Info: Processing ended: Mon Jun 27 23:31:51 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:20 " "Info: Elapsed time: 00:00:20" {  } {  } 0}  } {  } 0}