pc2fpga.map.rpt

this is a sample about usb out transmission

Analysis & Synthesis report for pc2fpga
Mon Jun 27 23:31:30 2005
Version 5.0 Build 148 04/26/2005 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. State Machine - |pc2fpga|STATE
  9. General Register Statistics
 10. Inverted Register Statistics
 11. Multiplexer Restructuring Statistics (Restructuring Performed)
 12. Parameter Settings for User Entity Instance: Top-level Entity: |pc2fpga
 13. Parameter Settings for Inferred Entity Instance: sld_signaltap:auto_signaltap_0
 14. Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst
 15. SignalTap II Logic Analyzer Settings
 16. Analysis & Synthesis Equations
 17. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                           ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Mon Jun 27 23:31:30 2005    ;
; Quartus II Version          ; 5.0 Build 148 04/26/2005 SJ Full Version ;
; Revision Name               ; pc2fpga                                  ;
; Top-level Entity Name       ; pc2fpga                                  ;
; Family                      ; Cyclone                                  ;
; Total logic elements        ; 404                                      ;
; Total pins                  ; 19                                       ;
; Total virtual pins          ; 0                                        ;
; Total memory bits           ; 14,336                                   ;
; Total PLLs                  ; 0                                        ;
+-----------------------------+------------------------------------------+


+---------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                     ;
+--------------------------------------------------------------------+--------------+---------------+
; Option                                                             ; Setting      ; Default Value ;
+--------------------------------------------------------------------+--------------+---------------+
; Device                                                             ; EP1C12Q240C8 ;               ;
; Top-level entity name                                              ; pc2fpga      ; pc2fpga       ;
; Family name                                                        ; Cyclone      ; Stratix       ;