pc2fpga.stp

this is a sample about usb out transmission

<session jtag_chain="ByteBlasterII [LPT1]" jtag_device="@1: EP1C12 (0x020830DD)" sof_file="">
  <display_tree gui_logging_enabled="0">
    <display_branch instance="auto_signaltap_0" log="USE_GLOBAL_TEMP" signal_set="USE_GLOBAL_TEMP" trigger="USE_GLOBAL_TEMP"/>
  </display_tree>
  <instance entity_name="sld_signaltap" is_auto_node="yes" is_expanded="true" name="auto_signaltap_0" source_file="sld_signaltap.vhd">
    <node_ip_info instance_id="0" mfg_id="110" node_id="0" version="3"/>
    <signal_set global_temp="1" is_expanded="true" name="signal_set: 2005/05/07 23:26:59  #0">
      <clock name="clkin" polarity="posedge"/>
      <config ram_type="M4K" reserved_data_nodes="0" reserved_trigger_nodes="0" sample_depth="1024" trigger_in_enable="yes" trigger_in_node="fifo_empty" trigger_out_enable="no"/>
      <top_entity/>
      <signal_vec>
        <trigger_input_vec>
          <wire connection_status="true" name="fifo_data[0]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="fifo_data[1]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="fifo_data[2]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="fifo_data[3]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="fifo_data[4]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="fifo_data[5]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="fifo_data[6]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="fifo_data[7]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="fifo_empty" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="fifo_full" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="fifo_pf" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="fifo_rd" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="fifo_wr" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="rst" tap_mode="classic" type="input pin"/>
        </trigger_input_vec>
        <data_input_vec>
          <wire connection_status="true" name="fifo_data[0]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="fifo_data[1]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="fifo_data[2]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="fifo_data[3]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="fifo_data[4]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="fifo_data[5]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="fifo_data[6]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="fifo_data[7]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="fifo_empty" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="fifo_full" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="fifo_pf" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="fifo_rd" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="fifo_wr" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="rst" tap_mode="classic" type="input pin"/>
        </data_input_vec>
      </signal_vec>
      <presentation>
        <setup_view>
          <bus is_signal_inverted="no" link="all" name="fifo_data" order="msb_to_lsb" radix="hex" state="collapse" type="output pin">
            <net is_signal_inverted="no" name="fifo_data[7]"/>
            <net is_signal_inverted="no" name="fifo_data[6]"/>
            <net is_signal_inverted="no" name="fifo_data[5]"/>
            <net is_signal_inverted="no" name="fifo_data[4]"/>
            <net is_signal_inverted="no" name="fifo_data[3]"/>
            <net is_signal_inverted="no" name="fifo_data[2]"/>
            <net is_signal_inverted="no" name="fifo_data[1]"/>
            <net is_signal_inverted="no" name="fifo_data[0]"/>