📄 tinyplc.h
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#define DIG_IN_7 PINC.7
#define DIG_IN_8 PIND.0
#define DIG_IN_9 PIND.1
#define DIG_IN_10 PIND.2
#define DIG_IN_11 PIND.3
#define DIG_IN_12 PIND.4
#define DIG_IN_13 PIND.5
#define DIG_IN_14 PIND.6
#define DIG_IN_15 PIND.7
#define DIG_IN_16 PING.5
#define DIG_IN_17 PING.1
#define DIG_IN_18 PING.2
#define DIG_IN_19 PING.3
#define DIG_IN_20 PING.4
#define TOTAL_INPUTS 21
#define DIG_OUT_0 PORTA.0
#define DIG_OUT_1 PORTA.1
#define DIG_OUT_2 PORTA.2
#define DIG_OUT_3 PORTA.3
#define DIG_OUT_4 PORTA.4
#define DIG_OUT_5 PORTA.5
#define DIG_OUT_6 PORTA.6
#define DIG_OUT_7 PORTA.7
#define DIG_OUT_8 PORTB.0
#define DIG_OUT_9 PORTB.1
#define DIG_OUT_10 PORTB.2
#define DIG_OUT_11 PORTB.3
#define DIG_OUT_12 PORTB.4
#define DIG_OUT_13 PORTB.5
#define DIG_OUT_14 PORTB.6
#define DIG_OUT_15 PORTB.7
#define DIG_OUT_16 PORTE.3
#define DIG_OUT_17 PORTE.4
#define DIG_OUT_18 PORTE.5
#define DIG_OUT_19 PORTE.6
#define DIG_OUT_20 PORTE.7
#define TOTAL_OUTPUTS 21
#define DEFAULT_BAUDRATE 9600
#define TXBUF_SIZE 128
#define RXBUF_SIZE 128
#define UBRR_VALUE (((XTAL / (8 * DEFAULT_BAUDRATE) + 1) / 2) - 1)
#define FRAMING_ERROR 0b00010000 /* bit 4 */
#define UCSR0B_OFF 0b00000000 /* everything off */
#define UCSR0B_INIT 0b10010000
/* 1....... RXCIE0 enable RX complete interrupt
* .0...... TXCIE0 disable TX complete interrupt
* ..0..... UDRIE0 enable Data Register Empty interrupt
* ...1.... RXEN0 enable receiver
* ....0... TXEN0 disable TX until we have data to transmit
* .....0.. UCSZ02 high bit of dataformat select (only
* needed for 9-bit data formats)
* ......0. RXB80 Received 9th data bit (read-only)
* .......0 TXB80 Transmitted 9th data bit
*/
#define XMIT_ENABLE 0b00001000
/* ....1... TXEN0 enable TX */
#define UDRI_ENABLE 0b00100000
/* ..1..... UDRIE0 enable Data Register Empty Interrupt */
#define TXCI_ENABLE 0b01000000
/* .10..... TXCIE0 enable TX complete Interrupt */
#define UCSR0B_XMIT (UCSR0B_INIT | XMIT_ENABLE | UDRI_ENABLE)
#define UCSR0B_FINISH (UCSR0B_INIT | XMIT_ENABLE | TXCI_ENABLE)
#define UCSR0C_INIT 0b00000110
/* 00...... UMSEL01:UMSEL00 Asynchronous USART
* ..00.... UPM01:UPM00 disable parity
* ....0... USBS0 one stop bit
* .....11. UCSZ01:UCSZ00 character size = 8 bits
* .......0 UCPOL0 clock polarity (don't care for ASYNC)
*/
#define ADMUX_VALUE 0b00000000
/* 00...... REFS1:REFS0 use AREF as reference, internal VREF OF
* ..0..... ADLAR is 0, right-justify ADC result
* ...00000 MUX4:0 ADC channel 0, not differential, no gain
*/
#ifdef ENABLE_JTAG
#define DIDR0_VALUE 0b00001111 /* disable A0 input, it's analog input */
#else
#define DIDR0_VALUE 0b11111111 /* disable A0 input, it's analog input */
#endif
#define ADC_CLK_MAX 192000L /* must be between 50K and 200K */
#if (XTAL / 2) < ADC_CLK_MAX
#define ADCSRA_INIT 0b10000000
/* 1....... ADEN ADC enabled
* .0...... ADSC start conversion
* ..0..... ADATE ADC auto trigger
* ...0.... ADIF interrupt flag
* ....0... ADIE
* .....000 ADPS2:0 prescalar = 2
*/
#define ADC_CLK_DIVISOR 2
#else
#if (XTAL / 4) < ADC_CLK_MAX
#define ADCSRA_INIT 0b10000010
/* 1....... ADEN ADC enabled
* .0...... ADSC start conversion
* ..0..... ADATE ADC auto trigger
* ...0.... ADIF interrupt flag
* ....0... ADIE
* .....010 ADPS2:0 prescalar = 4
*/
#define ADC_CLK_DIVISOR 4
#else
#if (XTAL / 8) < ADC_CLK_MAX
#define ADCSRA_INIT 0b10000011
/* 1....... ADEN ADC enabled
* .0...... ADSC start conversion
* ..0..... ADATE ADC auto trigger
* ...0.... ADIF interrupt flag
* ....0... ADIE
* .....011 ADPS2:0 prescalar = 8
*/
#define ADC_CLK_DIVISOR 8
#else
#if (XTAL / 16) < ADC_CLK_MAX
#define ADCSRA_INIT 0b10000100
/* 1....... ADEN ADC enabled
* .0...... ADSC start conversion
* ..0..... ADATE ADC auto trigger
* ...0.... ADIF interrupt flag
* ....0... ADIE
* .....100 ADPS2:0 prescalar = 16
*/
#define ADC_CLK_DIVISOR 16
#else
#if (XTAL / 32) < ADC_CLK_MAX
#define ADCSRA_INIT 0b10000101
/* 1....... ADEN ADC enabled
* .0...... ADSC start conversion
* ..0..... ADATE ADC auto trigger
* ...0.... ADIF interrupt flag
* ....0... ADIE
* .....101 ADPS2:0 prescalar = 32
*/
#define ADC_CLK_DIVISOR 32
#else
#if (XTAL / 64) < ADC_CLK_MAX
#define ADCSRA_INIT 0b10000110
/* 1....... ADEN ADC enabled
* .0...... ADSC start conversion
* ..0..... ADATE ADC auto trigger
* ...0.... ADIF interrupt flag
* ....0... ADIE
* .....110 ADPS2:0 prescalar = 64
*/
#define ADC_CLK_DIVISOR 64
#else
#if (XTAL / 128) < ADC_CLK_MAX
#define ADCSRA_INIT 0b10000111
/* 1....... ADEN ADC enabled
* .0...... ADSC start conversion
* ..0..... ADATE ADC auto trigger
* ...0.... ADIF interrupt flag
* ....0... ADIE
* .....111 ADPS2:0 prescalar = 128
*/
#define ADC_CLK_DIVISOR 128
#else
#error Cannot get ADC prescalar for this XTAL
#endif /* 128 */
#endif /* 64 */
#endif /* 32 */
#endif /* 16 */
#endif /* 8 */
#endif /* 4 */
#endif /* 2 */
#define ADCSRA_ADSC 0b01000000
/* .1...... ADSC: start conversion becomes 0 when ADC done */
#define ADCSRA_GO (ADCSRA_INIT | ADCSRA_ADSC)
#define ADC_CONVERSION_TIME (((ADC_CLK_DIVISOR * 13L + (TMR0_CYCLES / 2)) / TMR0_CYCLES) + 1)
#define ADC_FILTER_STRENGTH 4 /* must be a power of 2 */
#if (ADC_FILTER_STRENGTH != 2) && (ADC_FILTER_STRENGTH != 4) && (ADC_FILTER_STRENGTH != 8) && (ADC_FILTER_STRENGTH != 16) && (ADC_FILTER_STRENGTH != 32)
#error ADC_FILTER_STRENGTH must be a power of 2 (2, 4, 8, 16, 32)
#endif
#define ADC_FILTER_ROUNDING (ADC_FILTER_STRENGTH / 2)
#define EI() #asm(" sei")
#define DI() #asm(" cli")
#define PET_WATCHDOG() #asm(" wdr")
typedef unsigned char BYTE;
typedef unsigned short WORD;
typedef unsigned long DWORD;
typedef unsigned long RTC_T;
#if HEARTBEAT_FREQUENCY == 1000
#define MSECS_TO_TICKS(MSEC) (MSEC)
#else
#define MSECS_TO_TICKS(MSEC) (((MSEC) * 1000 + (HEARTBEAT_FREQUENCY / 2)) / (HEARTBEAT_FREQUENCY))
#endif
#define RTC() (tick_counter)
#ifndef TRUE
#define TRUE 1
#endif
#ifndef FALSE
#define FALSE 0
#endif
#ifndef ON
#define ON 1
#endif
#ifndef OFF
#define OFF 0
#endif
#include "plcshare.h"
#endif /* TINYPLC_H_ */
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