fpgatodsp.v

用于FPGA向DSP传送数据的接口

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    22:28:19 08/14/07
// Design Name:    
// Module Name:    fpgatodsp
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module fpgatodsp(CLK,RST,DA_CLK,daout,addr,nrd,nwr,ce2,dout,interrupt,NOE,test);
 input CLK;
 input RST;
 input nrd;
 input nwr;
 output wire [8:1]test;
 input NOE;
 output reg [11:0]daout;
 input [19:0]addr;
 input ce2;
 inout [31:0]dout;
 reg [31:0]dout_reg;
// reg [31:0]dout;
 output reg interrupt;

output wire DA_CLK;
assign DA_CLK=CLK;

assign test[1]=addr[0];

//assign dout=(~NOE)?dout_reg:'bz;

assign test[2]=dout_reg[30];
assign test[3]=dout_reg[28];
assign test[4]=dout_reg[26];
assign test[5]=dout_reg[18];
assign test[6]=dout_reg[14];
assign test[7]=dout_reg[12];
assign test[8]=dout_reg[8];

 reg [10:0]cnt;
 always@(posedge CLK)begin
  if(RST)begin
   cnt<=0;
	interrupt<=0;
  end
  else begin
   if(cnt==163)begin
	 cnt<=0;
	 interrupt<=~interrupt;			//100K
	end
	else begin
	 cnt<=cnt+1;
	end
  end
 end

reg [31:0]xc1out=-32'd70;
reg [31:0]xc1out1=-32'd30;
reg [31:0]xc1out2=-32'd10;
reg [31:0]xc2out=32'd30;				  //-1/16
reg [31:0]xc2out1=32'd50;
reg [31:0]xc2out2=32'd90;

always@(negedge interrupt)begin
// if(!ce2)begin
// case(addr[19:0])
//  //20'h00000:dout_reg[31:0]=xc1out[31:0];
//  20'h00001:dout_reg[31:0]<=xc1out[31:0];
//  20'h00010:dout_reg[31:0]<=xc1out1[31:0];
//  20'h00011:dout_reg[31:0]<=xc1out2[31:0];
//  20'h00100:dout_reg[31:0]<=xc2out[31:0];
//  20'h00101:dout_reg[31:0]<=xc2out1[31:0];
//  20'h00110:dout_reg[31:0]<=xc2out2[31:0];
//  default:dout_reg[31:0]<='bx;
//  endcase
// end
 dout_reg[31:0]<=xc1out[31:0];
 xc1out[31:0]<=xc1out1[31:0];
 xc1out1[31:0]<=xc1out2[31:0];
 xc1ou2[31:0]<=xc2out[31:0];
 xc2out[31:0]<=xc2out1[31:0];
 xc2out1[31:0]<=xc2out2[31:0];

end


always@(negedge nwr)begin
 if(!ce2)begin
  daout[11:0]<=dout[15:4];
 end
end

endmodule