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📄 fpgatodsp.twr

📁 用于FPGA向DSP传送数据的接口
💻 TWR
字号:
--------------------------------------------------------------------------------
Release 7.1.04i Trace H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

D:/xilinx/bin/nt/trce.exe -ise d:\favorites\fpgadsp\fpgatodsp.ise -intstyle ise
-e 3 -l 3 -s 12 -xml fpgatodsp fpgatodsp.ncd -o fpgatodsp.twr fpgatodsp.pcf


Design file:              fpgatodsp.ncd
Physical constraint file: fpgatodsp.pcf
Device,speed:             xc4vsx35,-12 (PREVIEW 1.57 2005-08-24, STEPPING level 1)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock CLK
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
RST         |   -0.619(R)|    2.671(R)|DA_CLK_OBUF       |   0.000|
------------+------------+------------+------------------+--------+

Setup/Hold to clock nrd
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
addr<0>     |    3.859(F)|    2.096(F)|nrd_BUFGP         |   0.000|
addr<4>     |    3.280(F)|    2.371(F)|nrd_BUFGP         |   0.000|
addr<8>     |    3.439(F)|    2.278(F)|nrd_BUFGP         |   0.000|
ce2         |   -0.839(F)|    4.482(F)|nrd_BUFGP         |   0.000|
------------+------------+------------+------------------+--------+

Setup/Hold to clock nwr
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
ce2         |    0.093(F)|    2.180(F)|nwr_BUFGP         |   0.000|
dout<10>    |   -0.496(F)|    1.800(F)|nwr_BUFGP         |   0.000|
dout<11>    |   -0.605(F)|    1.900(F)|nwr_BUFGP         |   0.000|
dout<12>    |   -0.944(F)|    2.213(F)|nwr_BUFGP         |   0.000|
dout<13>    |   -0.618(F)|    1.913(F)|nwr_BUFGP         |   0.000|
dout<14>    |   -0.459(F)|    1.766(F)|nwr_BUFGP         |   0.000|
dout<15>    |   -0.756(F)|    2.031(F)|nwr_BUFGP         |   0.000|
dout<4>     |   -0.734(F)|    2.021(F)|nwr_BUFGP         |   0.000|
dout<5>     |   -0.780(F)|    2.062(F)|nwr_BUFGP         |   0.000|
dout<6>     |   -0.908(F)|    2.178(F)|nwr_BUFGP         |   0.000|
dout<7>     |   -1.187(F)|    2.435(F)|nwr_BUFGP         |   0.000|
dout<8>     |   -0.966(F)|    2.231(F)|nwr_BUFGP         |   0.000|
dout<9>     |   -0.856(F)|    2.130(F)|nwr_BUFGP         |   0.000|
------------+------------+------------+------------------+--------+

Clock CLK to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
interrupt   |   10.807(R)|DA_CLK_OBUF       |   0.000|
------------+------------+------------------+--------+

Clock nrd to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
dout<0>     |    9.623(F)|nrd_BUFGP         |   0.000|
dout<10>    |    9.654(F)|nrd_BUFGP         |   0.000|
dout<11>    |    9.644(F)|nrd_BUFGP         |   0.000|
dout<12>    |    9.629(F)|nrd_BUFGP         |   0.000|
dout<13>    |    9.644(F)|nrd_BUFGP         |   0.000|
dout<14>    |    9.633(F)|nrd_BUFGP         |   0.000|
dout<15>    |    9.662(F)|nrd_BUFGP         |   0.000|
dout<16>    |    9.638(F)|nrd_BUFGP         |   0.000|
dout<17>    |    9.660(F)|nrd_BUFGP         |   0.000|
dout<18>    |    9.633(F)|nrd_BUFGP         |   0.000|
dout<19>    |    9.640(F)|nrd_BUFGP         |   0.000|
dout<1>     |    9.633(F)|nrd_BUFGP         |   0.000|
dout<20>    |    9.656(F)|nrd_BUFGP         |   0.000|
dout<21>    |    9.656(F)|nrd_BUFGP         |   0.000|
dout<22>    |    9.644(F)|nrd_BUFGP         |   0.000|
dout<23>    |    9.656(F)|nrd_BUFGP         |   0.000|
dout<24>    |    9.322(F)|nrd_BUFGP         |   0.000|
dout<25>    |    9.328(F)|nrd_BUFGP         |   0.000|
dout<26>    |    9.642(F)|nrd_BUFGP         |   0.000|
dout<28>    |    9.297(F)|nrd_BUFGP         |   0.000|
dout<29>    |    9.303(F)|nrd_BUFGP         |   0.000|
dout<2>     |    9.634(F)|nrd_BUFGP         |   0.000|
dout<30>    |    9.299(F)|nrd_BUFGP         |   0.000|
dout<3>     |    9.634(F)|nrd_BUFGP         |   0.000|
dout<4>     |    9.642(F)|nrd_BUFGP         |   0.000|
dout<5>     |    9.633(F)|nrd_BUFGP         |   0.000|
dout<6>     |    9.640(F)|nrd_BUFGP         |   0.000|
dout<7>     |    9.633(F)|nrd_BUFGP         |   0.000|
dout<8>     |    9.654(F)|nrd_BUFGP         |   0.000|
dout<9>     |    9.652(F)|nrd_BUFGP         |   0.000|
test<2>     |    9.443(F)|nrd_BUFGP         |   0.000|
test<3>     |    9.430(F)|nrd_BUFGP         |   0.000|
test<4>     |    9.430(F)|nrd_BUFGP         |   0.000|
test<5>     |    9.421(F)|nrd_BUFGP         |   0.000|
test<6>     |    9.423(F)|nrd_BUFGP         |   0.000|
test<7>     |    9.431(F)|nrd_BUFGP         |   0.000|
test<8>     |    9.469(F)|nrd_BUFGP         |   0.000|
------------+------------+------------------+--------+

Clock nwr to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
daout<0>    |    9.297(F)|nwr_BUFGP         |   0.000|
daout<10>   |    9.274(F)|nwr_BUFGP         |   0.000|
daout<11>   |    9.226(F)|nwr_BUFGP         |   0.000|
daout<1>    |    9.298(F)|nwr_BUFGP         |   0.000|
daout<2>    |    9.285(F)|nwr_BUFGP         |   0.000|
daout<3>    |    9.286(F)|nwr_BUFGP         |   0.000|
daout<4>    |    9.270(F)|nwr_BUFGP         |   0.000|
daout<5>    |    9.283(F)|nwr_BUFGP         |   0.000|
daout<6>    |    9.275(F)|nwr_BUFGP         |   0.000|
daout<7>    |    9.278(F)|nwr_BUFGP         |   0.000|
daout<8>    |    9.277(F)|nwr_BUFGP         |   0.000|
daout<9>    |    9.275(F)|nwr_BUFGP         |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock CLK
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
CLK            |    3.011|         |         |         |
---------------+---------+---------+---------+---------+

Pad to Pad
---------------+---------------+---------+
Source Pad     |Destination Pad|  Delay  |
---------------+---------------+---------+
CLK            |DA_CLK         |    8.691|
NOE            |dout<0>        |    4.948|
NOE            |dout<10>       |    7.162|
NOE            |dout<11>       |    7.031|
NOE            |dout<12>       |    5.882|
NOE            |dout<13>       |    7.152|
NOE            |dout<14>       |    7.074|
NOE            |dout<15>       |    6.351|
NOE            |dout<16>       |    7.139|
NOE            |dout<17>       |    6.349|
NOE            |dout<18>       |    7.254|
NOE            |dout<19>       |    7.261|
NOE            |dout<1>        |    5.281|
NOE            |dout<20>       |    6.870|
NOE            |dout<21>       |    6.870|
NOE            |dout<22>       |    7.261|
NOE            |dout<23>       |    7.273|
NOE            |dout<24>       |    7.526|
NOE            |dout<25>       |    7.532|
NOE            |dout<26>       |    7.388|
NOE            |dout<27>       |    7.138|
NOE            |dout<28>       |    7.276|
NOE            |dout<29>       |    7.428|
NOE            |dout<2>        |    5.282|
NOE            |dout<30>       |    7.278|
NOE            |dout<31>       |    7.137|
NOE            |dout<3>        |    5.434|
NOE            |dout<4>        |    5.607|
NOE            |dout<5>        |    5.598|
NOE            |dout<6>        |    6.046|
NOE            |dout<7>        |    6.039|
NOE            |dout<8>        |    6.336|
NOE            |dout<9>        |    7.039|
addr<0>        |test<1>        |    6.791|
---------------+---------------+---------+

Analysis completed Thu Aug 16 10:31:26 2007
--------------------------------------------------------------------------------



Peak Memory Usage: 183 MB

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