fpgatodsp.par

用于FPGA向DSP传送数据的接口

Release 7.1.04i par H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

WQ-98007498B40C::  Thu Aug 16 10:31:09 2007

par -w -intstyle ise -ol std -t 1 fpgatodsp_map.ncd fpgatodsp.ncd fpgatodsp.pcf


Constraints file: fpgatodsp.pcf.
Loading device for application Rf_Device from file '4vsx35.nph' in environment
D:/xilinx.
   "fpgatodsp" is an NCD, version 3.1, device xc4vsx35, package ff668, speed -12
This design is using the default stepping level (major silicon revision) for
this device (1). Unless your design is targeted at devices of this stepping
level, it is recommended that you explicitly specify the stepping level of the
parts you will be using. This will allow the tools to take advantage of any
available performance and functional enhancements for this device. The latest
stepping level for this device is '2'. Additional information on "stepping
level" is available at support.xilinx.com.

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.200 Volts. (default - Range: 1.140 to 1.260 Volts)


Device speed data version:  "PREVIEW 1.57 2005-08-24".


Device Utilization Summary:

   Number of BUFGs                     3 out of 32      9%
   Number of External IOBs            80 out of 448    17%
      Number of LOCed IOBs            80 out of 80    100%

   Number of OLOGICs                  49 out of 448    10%
   Number of Slices                   25 out of 15360   1%
      Number of SLICEMs                0 out of 7680    0%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)

WARNING:Par:276 - The signal addr<2>_IBUF has no load
WARNING:Par:276 - The signal addr<3>_IBUF has no load
WARNING:Par:276 - The signal addr<5>_IBUF has no load
WARNING:Par:276 - The signal addr<6>_IBUF has no load
WARNING:Par:276 - The signal addr<7>_IBUF has no load
WARNING:Par:276 - The signal addr<9>_IBUF has no load
WARNING:Par:276 - The signal addr<10>_IBUF has no load
WARNING:Par:276 - The signal addr<11>_IBUF has no load
WARNING:Par:276 - The signal addr<12>_IBUF has no load
WARNING:Par:276 - The signal addr<13>_IBUF has no load
WARNING:Par:276 - The signal addr<14>_IBUF has no load
WARNING:Par:276 - The signal addr<15>_IBUF has no load
WARNING:Par:276 - The signal addr<16>_IBUF has no load
WARNING:Par:276 - The signal addr<17>_IBUF has no load
WARNING:Par:276 - The signal addr<18>_IBUF has no load
WARNING:Par:276 - The signal addr<19>_IBUF has no load
WARNING:Par:276 - The signal addr<1>_IBUF has no load

Starting Placer

Phase 1.1
Phase 1.1 (Checksum:989919) REAL time: 4 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 4 secs 

Phase 3.2
......
WARNING:Place:644 - A clock IOB  clock component is not placed at an optimal
   clock IOB site  The clock IOB component <nrd> is placed at site IOB_X0Y131.
   The clock IO site can use the fast path between the IO and the Clock
   buffer/GCLK if the IOB is placed in the master Clock IOB Site. This is
   normally an ERROR but the environment variable
   XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING is set allowing your design to continue.
WARNING:Place:644 - A clock IOB  clock component is not placed at an optimal
   clock IOB site  The clock IOB component <nwr> is placed at site IOB_X0Y128.
   The clock IO site can use the fast path between the IO and the Clock
   buffer/GCLK if the IOB is placed in the master Clock IOB Site. This is
   normally an ERROR but the environment variable
   XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING is set allowing your design to continue.
WARNING:Place:644 - A clock IOB  clock component is not placed at an optimal
   clock IOB site  The clock IOB component <CLK> is placed at site IOB_X1Y58.
   The clock IO site can use the fast path between the IO and the Clock
   buffer/GCLK if the IOB is placed in the master Clock IOB Site. This is
   normally an ERROR but the environment variable
   XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING is set allowing your design to continue.


Phase 3.2 (Checksum:98a813) REAL time: 5 secs 

Phase 4.30
Phase 4.30 (Checksum:26259fc) REAL time: 5 secs 

Phase 5.3
Phase 5.3 (Checksum:2faf07b) REAL time: 5 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 5 secs 

Phase 7.8
.
Phase 7.8 (Checksum:a11c87) REAL time: 5 secs 

Phase 8.5
Phase 8.5 (Checksum:4c4b3f8) REAL time: 5 secs 

Phase 9.18
Phase 9.18 (Checksum:55d4a77) REAL time: 5 secs 

Phase 10.27
Phase 10.27 (Checksum:5f5e0f6) REAL time: 5 secs 

Phase 11.5
Phase 11.5 (Checksum:68e7775) REAL time: 5 secs 

Writing design to file fpgatodsp.ncd


Total REAL time to Placer completion: 5 secs 
Total CPU time to Placer completion: 5 secs 

Starting Router

Phase 1: 398 unrouted;       REAL time: 6 secs 

Phase 2: 308 unrouted;       REAL time: 7 secs 

Phase 3: 31 unrouted;       REAL time: 7 secs 

Phase 4: 0 unrouted;       REAL time: 7 secs 

Total REAL time to Router completion: 7 secs 
Total CPU time to Router completion: 7 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|           nwr_BUFGP |BUFGCTRL_X0Y26| No   |   12 |  0.048     |  2.248      |
+---------------------+--------------+------+------+------------+-------------+
|           nrd_BUFGP |BUFGCTRL_X0Y25| No   |   37 |  0.321     |  2.361      |
+---------------------+--------------+------+------+------------+-------------+
|         DA_CLK_OBUF | BUFGCTRL_X0Y6| No   |    8 |  0.100     |  2.087      |
+---------------------+--------------+------+------+------------+-------------+

INFO:Par:340 - 
   The Delay report will not be generated when running non-timing driven PAR
   with effort level Standard or Medium. If a delay report is required please do
   one of the following:  1) use effort level High, 2) use the following
   environment variable "XIL_PAR_GENERATE_DLY_REPORT", 3) create Timing
   constraints for the design.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 10 secs 
Total CPU time to PAR completion: 9 secs 

Peak Memory Usage:  176 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 20
Number of info messages: 1

Writing design to file fpgatodsp.ncd



PAR done!