📄 fpgatodsp.mrp
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| addr<4> | IOB | INPUT | LVCMOS25 | | | | | || addr<5> | IOB | INPUT | LVCMOS25 | | | | | || addr<6> | IOB | INPUT | LVCMOS25 | | | | | || addr<7> | IOB | INPUT | LVCMOS25 | | | | | || addr<8> | IOB | INPUT | LVCMOS25 | | | | | || addr<9> | IOB | INPUT | LVCMOS25 | | | | | || addr<10> | IOB | INPUT | LVCMOS25 | | | | | || addr<11> | IOB | INPUT | LVCMOS25 | | | | | || addr<12> | IOB | INPUT | LVCMOS25 | | | | | || addr<13> | IOB | INPUT | LVCMOS25 | | | | | || addr<14> | IOB | INPUT | LVCMOS25 | | | | | || addr<15> | IOB | INPUT | LVCMOS25 | | | | | || addr<16> | IOB | INPUT | LVCMOS25 | | | | | || addr<17> | IOB | INPUT | LVCMOS25 | | | | | || addr<18> | IOB | INPUT | LVCMOS25 | | | | | || addr<19> | IOB | INPUT | LVCMOS25 | | | | | || ce2 | IOB | INPUT | LVCMOS25 | | | | | || daout<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | || daout<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | || daout<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | || daout<3> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | || daout<4> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | || daout<5> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | || daout<6> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | || daout<7> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | || daout<8> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | || daout<9> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | || daout<10> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | || daout<11> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | || dout<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | || dout<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | || dout<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | || dout<3> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | || dout<4> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | OFF1 | | || dout<5> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | OFF1 | | || dout<6> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | OFF1 | | || dout<7> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | OFF1 | | || dout<8> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | OFF1 | | || dout<9> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | OFF1 | | || dout<10> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | OFF1 | | || dout<11> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | OFF1 | | || dout<12> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | OFF1 | | || dout<13> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | OFF1 | | || dout<14> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | OFF1 | | || dout<15> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | OFF1 | | || dout<16> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | || dout<17> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | || dout<18> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | || dout<19> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | || dout<20> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | || dout<21> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | || dout<22> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | || dout<23> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | || dout<24> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | || dout<25> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | || dout<26> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | || dout<27> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || dout<28> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | || dout<29> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | || dout<30> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | || dout<31> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || interrupt | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || nrd | IOB | INPUT | LVCMOS25 | | | | | || nwr | IOB | INPUT | LVCMOS25 | | | | | || test<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || test<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | || test<3> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | || test<4> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | || test<5> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | || test<6> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | || test<7> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | || test<8> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | |+----------------------------------------------------------------------------------------------------------------------------------------+Section 7 - RPMs----------------Section 8 - Guide Report------------------------Guide not run on this design.Section 9 - Area Group Summary------------------------------No area groups were found in this design.Section 10 - Modular Design Summary-----------------------------------Modular Design not used for this design.Section 11 - Timing Report--------------------------This design was not run using timing mode.Section 12 - Configuration String Details--------------------------Use the "-detail" map option to print out Configuration StringsSection 13 - Additional Device Resource Counts----------------------------------------------Number of JTAG Gates for IOBs = 80Number of Equivalent Gates for Design = 842Number of RPM Macros = 0Number of Hard Macros = 0PMV = 0USR_ACCESS_VIRTEX4 = 0BUFIO = 0GT11CLK = 0GT11 = 0IDELAYCTRL = 0FRAME_ECC_VIRTEX4 = 0STARTUP_VIRTEX4 = 0JTAGPPC = 0ICAP_VIRTEX4 = 0DPM = 0DCI_TEST = 0DCIRESET = 0CAPTURE_VIRTEX4 = 0BSCAN_VIRTEX4 = 0OSERDES = 0ISERDES = 0BUFR = 0EMAC = 0PPC405_ADV = 0MONITOR = 0PMCD = 0DCM_ADV = 0DSP48 = 0Unbonded IOBs = 0Bonded IOBs = 80XORs = 10CARRY_INITs = 6CARRY_SKIPs = 0CARRY_MUXes = 10Shift Registers = 0Static Shift Registers = 0Dynamic Shift Registers = 016x1 ROMs = 016x1 RAMs = 032x1 RAMs = 0Dual Port RAMs = 0MUXFs = 0MULT_ANDs = 04 input LUTs used as Route-Thrus = 64 input LUTs = 33Slice Latches not driven by LUTs = 0Slice Latches = 0Slice Flip Flops not driven by LUTs = 1Slice Flip Flops = 12SliceMs = 0SliceLs = 25Slices = 25F6 Muxes = 0F5 Muxes = 0F8 Muxes = 0F7 Muxes = 0Number of LUT signals with 4 loads = 0Number of LUT signals with 3 loads = 2Number of LUT signals with 2 loads = 7Number of LUT signals with 1 load = 21NGM Average fanout of LUT = 1.94NGM Maximum fanout of LUT = 12NGM Average fanin for LUT = 2.9394Number of LUT symbols = 33⌨️ 快捷键说明
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