fpgatodsp.mrp

用于FPGA向DSP传送数据的接口

Release 7.1.04i Map H.42
Xilinx Mapping Report File for Design 'fpgatodsp'

Design Information
------------------
Command Line   : D:/xilinx/bin/nt/map.exe -ise
d:\favorites\fpgadsp\fpgatodsp.ise -intstyle ise -p xc4vsx35-ff668-12 -cm area
-pr b -k 4 -c 100 -o fpgatodsp_map.ncd fpgatodsp.ngd fpgatodsp.pcf 
Target Device  : xc4vsx35
Target Package : ff668
Target Speed   : -12
Mapper Version : virtex4 -- $Revision: 1.26.6.4 $
Mapped Date    : Thu Aug 16 10:30:55 2007

Design Summary
--------------
Number of errors:      0
Number of warnings:   19
Logic Utilization:
  Number of Slice Flip Flops:          12 out of  30,720    1%
  Number of 4 input LUTs:              33 out of  30,720    1%
Logic Distribution:
  Number of occupied Slices:                           25 out of  15,360    1%
    Number of Slices containing only related logic:      25 out of      25  100%
    Number of Slices containing unrelated logic:          0 out of      25    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:             39 out of  30,720    1%
  Number used as logic:                 33
  Number used as a route-thru:           6
  Number of bonded IOBs:               80 out of     448   17%
  Number of BUFG/BUFGCTRLs:             3 out of      32    9%
    Number used as BUFGs:                3
    Number used as BUFGCTRLs:            0

Total equivalent gate count for design:  842
Additional JTAG gate count for IOBs:  3,840
Peak Memory Usage:  202 MB

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report
Section 12 - Configuration String Information
Section 13 - Additional Device Resource Counts

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------
WARNING:LIT:243 - Logical network addr<19>_IBUF has no load.
WARNING:LIT:374 - The above warning message base_net_load_rule is repeated 16
   more times for the following (max. 5 shown):
   addr<18>_IBUF,
   addr<17>_IBUF,
   addr<16>_IBUF,
   addr<15>_IBUF,
   addr<14>_IBUF
   To see the details of these warning messages, please use the -detail switch.
WARNING:PhysDesignRules:367 - The signal <addr<2>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <addr<3>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <addr<5>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <addr<6>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <addr<7>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <addr<9>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <addr<10>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <addr<11>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <addr<12>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <addr<13>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <addr<14>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <addr<15>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <addr<16>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <addr<17>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <addr<18>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <addr<19>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <addr<1>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.

Section 3 - Informational
-------------------------
INFO:MapLib:562 - No environment variables are currently set.
INFO:MapLib:742 - Your design is targeting LX/SX Production Step 0/1/ES devices.
   Please note that there are new specifications for the DCMs to guarantee
   maximum frequency performance. If the DCM input clock might stop or if the
   DCM reset might be asserted for an extended time, then use of the dcm_standby
   macro may be required. Please see Answer Record 21127.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
   rate limited output drivers. The delay on speed critical single ended outputs
   can be dramatically reduced by designating them as fast outputs in the
   schematic.

Section 4 - Removed Logic Summary
---------------------------------
   2 block(s) optimized away

Section 5 - Removed Logic
-------------------------

Optimized Block(s):
TYPE 		BLOCK
GND 		XST_GND
VCC 		XST_VCC

To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.

Section 6 - IOB Properties
--------------------------

+----------------------------------------------------------------------------------------------------------------------------------------+
| IOB Name                           | Type             | Direction | IO Standard | Drive    | Slew | Reg (s)      | Resistor | IOB      |
|                                    |                  |           |             | Strength | Rate |              |          | Delay    |
+----------------------------------------------------------------------------------------------------------------------------------------+
| CLK                                | IOB              | INPUT     | LVCMOS25    |          |      |              |          |          |
| DA_CLK                             | IOB              | OUTPUT    | LVCMOS25    | 12       | SLOW |              |          |          |
| NOE                                | IOB              | INPUT     | LVCMOS25    |          |      |              |          |          |
| RST                                | IOB              | INPUT     | LVCMOS25    |          |      |              |          |          |
| addr<0>                            | IOB              | INPUT     | LVCMOS25    |          |      |              |          |          |
| addr<1>                            | IOB              | INPUT     | LVCMOS25    |          |      |              |          |          |
| addr<2>                            | IOB              | INPUT     | LVCMOS25    |          |      |              |          |          |
| addr<3>                            | IOB              | INPUT     | LVCMOS25    |          |      |              |          |          |