fpgatodsp.syr

用于FPGA向DSP传送数据的接口

# FlipFlops/Latches                : 61
#      FD                          : 11
#      FDE_1                       : 49
#      FDRE                        : 1
# Clock Buffers                    : 3
#      BUFGP                       : 3
# IO Buffers                       : 60
#      IBUF                        : 6
#      IOBUF                       : 12
#      OBUF                        : 22
#      OBUFT                       : 20
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 4vsx35ff668-12 

 Number of Slices:                      42  out of  15360     0%  
 Number of Slice Flip Flops:            61  out of  30720     0%  
 Number of 4 input LUTs:                42  out of  30720     0%  
 Number of bonded IOBs:                 80  out of    450    17%  
 Number of GCLKs:                        3  out of     32     9%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
nrd                                | BUFGP                  | 37    |
nwr                                | BUFGP                  | 12    |
CLK                                | BUFGP                  | 12    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -12

   Minimum period: 2.753ns (Maximum Frequency: 363.280MHz)
   Minimum input arrival time before clock: 2.954ns
   Maximum output required time after clock: 3.935ns
   Maximum combinational path delay: 4.876ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'CLK'
  Clock period: 2.753ns (frequency: 363.280MHz)
  Total number of paths / destination ports: 199 / 13
-------------------------------------------------------------------------
Delay:               2.753ns (Levels of Logic = 13)
  Source:            cnt_0 (FF)
  Destination:       cnt_10 (FF)
  Source Clock:      CLK rising
  Destination Clock: CLK rising

  Data Path: cnt_0 to cnt_10
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               3   0.272   0.406  cnt_0 (cnt_0)
     INV:I->O              1   0.322   0.000  fpgatodsp_cnt__n0000<0>lut_INV_0 (N3)
     MUXCY:S->O            1   0.278   0.000  fpgatodsp_cnt__n0000<0>cy (fpgatodsp_cnt__n0000<0>_cyo)
     MUXCY:CI->O           1   0.034   0.000  fpgatodsp_cnt__n0000<1>cy (fpgatodsp_cnt__n0000<1>_cyo)
     MUXCY:CI->O           1   0.034   0.000  fpgatodsp_cnt__n0000<2>cy (fpgatodsp_cnt__n0000<2>_cyo)
     MUXCY:CI->O           1   0.034   0.000  fpgatodsp_cnt__n0000<3>cy (fpgatodsp_cnt__n0000<3>_cyo)
     MUXCY:CI->O           1   0.034   0.000  fpgatodsp_cnt__n0000<4>cy (fpgatodsp_cnt__n0000<4>_cyo)
     MUXCY:CI->O           1   0.034   0.000  fpgatodsp_cnt__n0000<5>cy (fpgatodsp_cnt__n0000<5>_cyo)
     MUXCY:CI->O           1   0.034   0.000  fpgatodsp_cnt__n0000<6>cy (fpgatodsp_cnt__n0000<6>_cyo)
     MUXCY:CI->O           1   0.034   0.000  fpgatodsp_cnt__n0000<7>cy (fpgatodsp_cnt__n0000<7>_cyo)
     MUXCY:CI->O           1   0.034   0.000  fpgatodsp_cnt__n0000<8>cy (fpgatodsp_cnt__n0000<8>_cyo)
     MUXCY:CI->O           0   0.034   0.000  fpgatodsp_cnt__n0000<9>cy (fpgatodsp_cnt__n0000<9>_cyo)
     XORCY:CI->O           1   0.273   0.451  fpgatodsp_cnt__n0000<10>_xor (cnt__n0000<10>)
     LUT3_L:I2->LO         1   0.147   0.000  cnt_101 (N82)
     FD:D                      0.297          cnt_10
    ----------------------------------------
    Total                      2.753ns (1.895ns logic, 0.858ns route)
                                       (68.8% logic, 31.2% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'nrd'
  Total number of paths / destination ports: 145 / 74
-------------------------------------------------------------------------
Offset:              2.954ns (Levels of Logic = 2)
  Source:            ce2 (PAD)
  Destination:       dout_reg_11 (FF)
  Destination Clock: nrd falling

  Data Path: ce2 to dout_reg_11
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   0.754   0.394  ce2_IBUF (ce2_IBUF)
     INV:I->O             49   0.322   0.922  daout_N01_INV_0 (daout_N0)
     FDE_1:CE                  0.562          dout_reg_0
    ----------------------------------------
    Total                      2.954ns (1.638ns logic, 1.316ns route)
                                       (55.4% logic, 44.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'nwr'
  Total number of paths / destination ports: 24 / 24
-------------------------------------------------------------------------
Offset:              2.954ns (Levels of Logic = 2)
  Source:            ce2 (PAD)
  Destination:       daout_11 (FF)
  Destination Clock: nwr falling

  Data Path: ce2 to daout_11
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   0.754   0.394  ce2_IBUF (ce2_IBUF)
     INV:I->O             49   0.322   0.922  daout_N01_INV_0 (daout_N0)
     FDE_1:CE                  0.562          daout_0
    ----------------------------------------
    Total                      2.954ns (1.638ns logic, 1.316ns route)
                                       (55.4% logic, 44.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'CLK'
  Total number of paths / destination ports: 12 / 12
-------------------------------------------------------------------------
Offset:              2.244ns (Levels of Logic = 1)
  Source:            RST (PAD)
  Destination:       interrupt (FF)
  Destination Clock: CLK rising

  Data Path: RST to interrupt
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            12   0.754   0.532  RST_IBUF (RST_IBUF)
     FDRE:R                    0.958          interrupt
    ----------------------------------------
    Total                      2.244ns (1.712ns logic, 0.532ns route)
                                       (76.3% logic, 23.7% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'nrd'
  Total number of paths / destination ports: 37 / 37
-------------------------------------------------------------------------
Offset:              3.881ns (Levels of Logic = 1)
  Source:            dout_reg_11_1 (FF)
  Destination:       dout<26> (PAD)
  Source Clock:      nrd falling

  Data Path: dout_reg_11_1 to dout<26>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE_1:C->Q            1   0.232   0.394  dout_reg_11_1 (dout_reg_11_1)
     OBUFT:I->O                3.255          dout_26_OBUFT (dout<26>)
    ----------------------------------------
    Total                      3.881ns (3.487ns logic, 0.394ns route)
                                       (89.8% logic, 10.2% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              3.935ns (Levels of Logic = 1)
  Source:            interrupt (FF)
  Destination:       interrupt (PAD)
  Source Clock:      CLK rising

  Data Path: interrupt to interrupt
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q             2   0.272   0.408  interrupt (interrupt_OBUF)
     OBUF:I->O                 3.255          interrupt_OBUF (interrupt)
    ----------------------------------------
    Total                      3.935ns (3.527ns logic, 0.408ns route)
                                       (89.6% logic, 10.4% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'nwr'
  Total number of paths / destination ports: 12 / 12
-------------------------------------------------------------------------
Offset:              3.881ns (Levels of Logic = 1)
  Source:            daout_11 (FF)
  Destination:       daout<11> (PAD)
  Source Clock:      nwr falling

  Data Path: daout_11 to daout<11>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE_1:C->Q            1   0.232   0.394  daout_11 (daout_11)
     OBUF:I->O                 3.255          daout_11_OBUF (daout<11>)
    ----------------------------------------
    Total                      3.881ns (3.487ns logic, 0.394ns route)
                                       (89.8% logic, 10.2% route)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 34 / 34
-------------------------------------------------------------------------
Delay:               4.876ns (Levels of Logic = 2)
  Source:            NOE (PAD)
  Destination:       dout<26> (PAD)

  Data Path: NOE to dout<26>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            32   0.754   0.867  NOE_IBUF (NOE_IBUF)
     OBUFT:T->O                3.255          dout_29_OBUFT (dout<29>)
    ----------------------------------------
    Total                      4.876ns (4.009ns logic, 0.867ns route)
                                       (82.2% logic, 17.8% route)

=========================================================================
CPU : 10.33 / 10.92 s | Elapsed : 10.00 / 11.00 s
 
--> 

Total memory usage is 206076 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :   10 (   0 filtered)
Number of infos    :    0 (   0 filtered)