fpgatodsp.syr

用于FPGA向DSP传送数据的接口

Release 7.1.04i - xst H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 0.55 s | Elapsed : 0.00 / 1.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.55 s | Elapsed : 0.00 / 1.00 s
 
--> Reading design: fpgatodsp.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "fpgatodsp.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "fpgatodsp"
Output Format                      : NGC
Target Device                      : xc4vsx35-12-ff668

---- Source Options
Top Module Name                    : fpgatodsp
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 32
Number of Regional Clock Buffers   : Default
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : fpgatodsp.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
use_dsp48                          : auto
Optimize Instantiated Primitives   : NO
use_clock_enable                   : Auto
use_sync_set                       : Auto
use_sync_reset                     : Auto
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "fpgatodsp.v"
Module <fpgatodsp> compiled
No errors in compilation
Analysis of file <"fpgatodsp.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <fpgatodsp>.
Module <fpgatodsp> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <fpgatodsp>.
    Related source file is "fpgatodsp.v".
WARNING:Xst:1778 - Inout <dout<31:16>> is assigned but never used.
WARNING:Xst:1778 - Inout <dout<3:0>> is assigned but never used.
WARNING:Xst:653 - Signal <xc2out> is used but never assigned. Tied to value 01000101011001111000100110101011.
WARNING:Xst:653 - Signal <xc1out> is used but never assigned. Tied to value 00010010001101000101011001111000.
WARNING:Xst:653 - Signal <xc1out1> is used but never assigned. Tied to value 00100011010001010110011110001001.
WARNING:Xst:653 - Signal <xc1out2> is used but never assigned. Tied to value 00110100010101100111100010011010.
WARNING:Xst:653 - Signal <xc2out1> is used but never assigned. Tied to value 01010110011110001001101010111100.
WARNING:Xst:653 - Signal <xc2out2> is used but never assigned. Tied to value 01100111100010011010101111001101.
    Found 1-bit register for signal <interrupt>.
    Found 12-bit register for signal <daout>.
    Found 32-bit tristate buffer for signal <dout>.
    Found 11-bit up counter for signal <cnt>.
    Found 32-bit register for signal <dout_reg>.
    Summary:
	inferred   1 Counter(s).
	inferred  45 D-type flip-flop(s).
	inferred  32 Tristate(s).
Unit <fpgatodsp> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
MAC inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
DSP optimizations ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 1
 11-bit up counter                 : 1
# Registers                        : 3
 1-bit register                    : 1
 12-bit register                   : 1
 32-bit register                   : 1
# Tristates                        : 1
 32-bit tristate buffer            : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch  <dout_reg_31> (without init value) has a constant value of 0 in block <fpgatodsp>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <dout_reg_27> (without init value) has a constant value of 0 in block <fpgatodsp>.
Register <dout_reg_28> equivalent to <dout_reg_20> has been removed
Register <dout_reg_30> equivalent to <dout_reg_15> has been removed
Register <dout_reg_24> equivalent to <dout_reg_16> has been removed
Register <dout_reg_20> equivalent to <dout_reg_12> has been removed
Register <dout_reg_29> equivalent to <dout_reg_13> has been removed
Register <dout_reg_8> equivalent to <dout_reg_0> has been removed
Register <dout_reg_16> equivalent to <dout_reg_0> has been removed
Register <dout_reg_17> equivalent to <dout_reg_1> has been removed
Register <dout_reg_19> equivalent to <dout_reg_2> has been removed
Register <dout_reg_26> equivalent to <dout_reg_11> has been removed
Register <dout_reg_25> equivalent to <dout_reg_9> has been removed
Register <dout_reg_12> equivalent to <dout_reg_4> has been removed
Register <dout_reg_21> equivalent to <dout_reg_5> has been removed

Optimizing unit <fpgatodsp> ...
Loading device for application Rf_Device from file '4vsx35.nph' in environment D:/xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block fpgatodsp, actual ratio is 0.
FlipFlop dout_reg_11 has been replicated 2 time(s) to handle iob=true attribute.
FlipFlop dout_reg_4 has been replicated 5 time(s) to handle iob=true attribute.
FlipFlop dout_reg_13 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop dout_reg_0 has been replicated 4 time(s) to handle iob=true attribute.
FlipFlop dout_reg_1 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop dout_reg_2 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop dout_reg_5 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop dout_reg_9 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop dout_reg_14 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop dout_reg_15 has been replicated 2 time(s) to handle iob=true attribute.
FlipFlop dout_reg_18 has been replicated 1 time(s) to handle iob=true attribute.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : fpgatodsp.ngr
Top Level Output File Name         : fpgatodsp
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 80

Macro Statistics :
# Registers                        : 4
#      1-bit register              : 1
#      11-bit register             : 1
#      12-bit register             : 1
#      32-bit register             : 1
# Tristates                        : 1
#      32-bit tristate buffer      : 1
# Adders/Subtractors               : 1
#      11-bit adder                : 1

Cell Usage :
# BELS                             : 67
#      GND                         : 1
#      INV                         : 3
#      LUT1_L                      : 10
#      LUT2                        : 3
#      LUT3                        : 15
#      LUT3_L                      : 11
#      LUT4                        : 2
#      LUT4_L                      : 1
#      MUXCY                       : 10
#      VCC                         : 1
#      XORCY                       : 10