fpgatodsp.drc

来自「用于FPGA向DSP传送数据的接口」· DRC 代码 · 共 36 行

DRC
36 行
字号 
WARNING:PhysDesignRules:367 - The signal <addr<2>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.WARNING:PhysDesignRules:367 - The signal <addr<3>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.WARNING:PhysDesignRules:367 - The signal <addr<5>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.WARNING:PhysDesignRules:367 - The signal <addr<6>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.WARNING:PhysDesignRules:367 - The signal <addr<7>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.WARNING:PhysDesignRules:367 - The signal <addr<9>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.WARNING:PhysDesignRules:367 - The signal <addr<10>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.WARNING:PhysDesignRules:367 - The signal <addr<11>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.WARNING:PhysDesignRules:367 - The signal <addr<12>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.WARNING:PhysDesignRules:367 - The signal <addr<13>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.WARNING:PhysDesignRules:367 - The signal <addr<14>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.WARNING:PhysDesignRules:367 - The signal <addr<15>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.WARNING:PhysDesignRules:367 - The signal <addr<16>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.WARNING:PhysDesignRules:367 - The signal <addr<17>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.WARNING:PhysDesignRules:367 - The signal <addr<18>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.WARNING:PhysDesignRules:367 - The signal <addr<19>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.WARNING:PhysDesignRules:367 - The signal <addr<1>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.DRC detected 0 errors and 17 warnings.

fpgatodsp.drc - 源码说明

本页面展示了「用于FPGA向DSP传送数据的接口」中的 fpgatodsp.drc 源码文件，采用 DRC 编程语言编写，共 36 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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