reg_data_out.v

来自「一个UART的FPGA core」· Verilog 代码 · 共 60 行

module reg_data_out(clk, csn,oe,addr,
               EF0,AE0,AF0,FF0,
               EF1,AE1,AF1,FF1,
               EF2,AE2,AF2,FF2,
               EF3,AE3,AF3,FF3,
               EF4,AE4,AF4,FF4,
               EF5,AE5,AF5,FF5,
               EF6,AE6,AF6,FF6,
               EF7,AE7,AF7,FF7,
	       datar_out0,datar_out1,datar_out2,datar_out3,
               data
                 );


input [4:0] addr;
input   csn,oe,clk;

input         EF0,AE0,AF0,FF0;
 input        EF1,AE1,AF1,FF1;
input         EF2,AE2,AF2,FF2;
 input        EF3,AE3,AF3,FF3;
input         EF4,AE4,AF4,FF4;
 input        EF5,AE5,AF5,FF5;
input         EF6,AE6,AF6,FF6;
input         EF7,AE7,AF7,FF7;
input[7:0] datar_out0;
input[7:0] datar_out1;
input[7:0] datar_out2;
input[7:0] datar_out3;

output[7:0]        data;
wire [4:0] addr;

assign data = fifot0 

always @(posedge clk )// read data
 if (!csn&oe)
   begin
    case(addr)
      5'd10 : data <= datar_out0;  //read receiver fifo 0
      5'd11 : data <= datar_out1;
      5'd12 : data <= datar_out2;
      5'd13 : data <= datar_out3;

      5'd16 : data <= { 4'b0, EF0, AE0, AF0, FF0 };//  read transmit fifo  0 interrupt status 
      5'd17 : data <= { 4'b0, EF1, AE1, AF1, FF1 };
      5'd18 : data <= { 4'b0, EF2, AE2, AF2, FF2 };
      5'd19 : data <= { 4'b0, EF3, AE3, AF3, FF3 };
      5'd20 : data <= { 4'b0, EF4, AE4, AF4, FF4  };
      5'd21 : data <= { 4'b0, EF5, AE5, AF5, FF5 };
      5'd22 : data <= { 4'b0, EF6, AE6, AF6, FF6  };
      5'd23 : data <= { 4'b0, EF7, AE7, AF7, FF7  };
  
     default: data <=8'bz;
 
    endcase
   end


endmodule