dpram16x8.naf

一个UART的FPGA core

WrAddress[3]  i
WrAddress[2]  i
WrAddress[1]  i
WrAddress[0]  i
Data[7]  i
Data[6]  i
Data[5]  i
Data[4]  i
Data[3]  i
Data[2]  i
Data[1]  i
Data[0]  i
WrClock  i
WE  i
WrClockEn  i
RdAddress[3]  i
RdAddress[2]  i
RdAddress[1]  i
RdAddress[0]  i
RdClock  i
RdClockEn  i
Reset  i
Q[7]  o
Q[6]  o
Q[5]  o
Q[4]  o
Q[3]  o
Q[2]  o
Q[1]  o
Q[0]  o