📄 automake.err
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***********************
Path information for path number 1:
Requested Period: 500.000
- Setup time: 0.324
= Required time: 499.676
- Propagation time: 6.884
= Slack (critical) : 492.792
Number of logic level(s): 4
Starting point: u12.intmask_2_.Q / Q
Ending point: u12.int_reg.Q / D
The start point is clocked by Uart4|clk [falling] on pin CK
The end point is clocked by Uart4|clk [rising] on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-----------------------------------------------------------------------------------
u12.intmask_2_.Q FD1P3AX Q Out 1.585 1.585 -
u12.intmask[2] Net - - - - 1
u12.fifot2_int ORCALUT4 C In 0.000 1.585 -
u12.fifot2_int ORCALUT4 Z Out 1.325 2.910 -
u12.fifot2_int Net - - - - 1
u12.int_regsr_2 ORCALUT4 C In 0.000 2.910 -
u12.int_regsr_2 ORCALUT4 Z Out 1.325 4.235 -
u12.int_regsr_2 Net - - - - 1
u12.int_regs_i ORCALUT4 D In 0.000 4.235 -
u12.int_regs_i ORCALUT4 Z Out 1.325 5.559 -
u12.int_regs_i Net - - - - 1
u12.int_reg.Q_0 ORCALUT4 A In 0.000 5.559 -
u12.int_reg.Q_0 ORCALUT4 Z Out 1.325 6.884 -
N_51 Net - - - - 1
u12.int_reg.Q FD1S3AX D In 0.000 6.884 -
===================================================================================
====================================
Detailed Report for Clock: Uart4|clk_in
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
------------------------------------------------------------------------------------------------------
u2.sys_clk_cnt_0_.Q Uart4|clk_in FD1S3DX Q u2.sys_clk_cnt[0] 1.880 990.597
u2.sys_clk_cnt_1_.Q Uart4|clk_in FD1S3DX Q u2.sys_clk_cnt[1] 1.842 990.635
u2.sys_clk_cnt_2_.Q Uart4|clk_in FD1S3DX Q u2.sys_clk_cnt[2] 1.842 990.846
u2.sys_clk_cnt_3_.Q Uart4|clk_in FD1S3DX Q u2.sys_clk_cnt[3] 1.842 990.846
u2.sys_clk_cnt_4_.Q Uart4|clk_in FD1S3DX Q u2.sys_clk_cnt[4] 1.842 991.057
u2.sys_clk_cnt_5_.Q Uart4|clk_in FD1S3DX Q u2.sys_clk_cnt[5] 1.842 991.057
u2.sys_clk_cnt_6_.Q Uart4|clk_in FD1S3DX Q u2.sys_clk_cnt[6] 1.880 991.230
u2.sys_clk_cnt_7_.Q Uart4|clk_in FD1S3DX Q u2.sys_clk_cnt[7] 1.880 991.230
u2.sys_clk_cnt_8_.Q Uart4|clk_in FD1S3BX Q u2.sys_clk_cnt[8] 1.880 994.058
======================================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
-------------------------------------------------------------------------------------------------------------------
u2.sys_clk_cnt_8_.Q Uart4|clk_in FD1S3BX D u2.sys_clk_cnt_5[8] 999.676 990.597
u2.sys_clk_cnt_7_.Q Uart4|clk_in FD1S3DX D u2.sys_clk_cnt_5[7] 999.676 990.808
u2.sys_clk_cnt_6_.Q Uart4|clk_in FD1S3DX D u2.un6_sys_clk_cnt_cry_6_0_S0 999.676 992.133
u2.sys_clk_cnt_4_.Q Uart4|clk_in FD1S3DX D u2.un6_sys_clk_cnt_cry_4_0_S0 999.676 992.344
u2.sys_clk_cnt_5_.Q Uart4|clk_in FD1S3DX D u2.un6_sys_clk_cnt_cry_4_0_S1 999.676 992.344
u2.sys_clk_cnt_2_.Q Uart4|clk_in FD1S3DX D u2.un6_sys_clk_cnt_cry_2_0_S0 999.676 992.555
u2.sys_clk_cnt_3_.Q Uart4|clk_in FD1S3DX D u2.un6_sys_clk_cnt_cry_2_0_S1 999.676 992.555
u2.sys_clk_cnt_1_.Q Uart4|clk_in FD1S3DX D u2.un6_sys_clk_cnt_cry_0_0_S1 999.676 995.383
u2.sys_clk_cnt_0_.Q Uart4|clk_in FD1S3DX D u2.sys_clk_cnt_i[0] 999.676 996.471
===================================================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 1000.000
- Setup time: 0.324
= Required time: 999.676
- Propagation time: 9.079
= Slack (non-critical) : 990.597
Number of logic level(s): 7
Starting point: u2.sys_clk_cnt_0_.Q / Q
Ending point: u2.sys_clk_cnt_8_.Q / D
The start point is clocked by Uart4|clk_in [rising] on pin CK
The end point is clocked by Uart4|clk_in [rising] on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-----------------------------------------------------------------------------------------------
u2.sys_clk_cnt_0_.Q FD1S3DX Q Out 1.880 1.880 -
u2.sys_clk_cnt[0] Net - - - - 4
u2.un6_sys_clk_cnt_axb_0 ORCALUT4 A In 0.000 1.880 -
u2.un6_sys_clk_cnt_axb_0 ORCALUT4 Z Out 1.325 3.204 -
u2.un6_sys_clk_cnt_axb_0 Net - - - - 1
u2.un6_sys_clk_cnt_cry_0_0 CCU2 A0 In 0.000 3.204 -
u2.un6_sys_clk_cnt_cry_0_0 CCU2 COUT1 Out 2.588 5.792 -
u2.un6_sys_clk_cnt_cry_1 Net - - - - 1
u2.un6_sys_clk_cnt_cry_2_0 CCU2 CIN In 0.000 5.792 -
u2.un6_sys_clk_cnt_cry_2_0 CCU2 COUT1 Out 0.211 6.003 -
u2.un6_sys_clk_cnt_cry_3 Net - - - - 1
u2.un6_sys_clk_cnt_cry_4_0 CCU2 CIN In 0.000 6.003 -
u2.un6_sys_clk_cnt_cry_4_0 CCU2 COUT1 Out 0.211 6.215 -
u2.un6_sys_clk_cnt_cry_5 Net - - - - 1
u2.un6_sys_clk_cnt_cry_6_0 CCU2 CIN In 0.000 6.215 -
u2.un6_sys_clk_cnt_cry_6_0 CCU2 COUT1 Out 0.211 6.426 -
u2.un6_sys_clk_cnt_cry_7 Net - - - - 1
u2.un6_sys_clk_cnt_s_8_0 CCU2 CIN In 0.000 6.426 -
u2.un6_sys_clk_cnt_s_8_0 CCU2 S0 Out 1.329 7.754 -
u2.un6_sys_clk_cnt_s_8_0_S0 Net - - - - 1
u2.sys_clk_cnt_5[8] ORCALUT4 A In 0.000 7.754 -
u2.sys_clk_cnt_5[8] ORCALUT4 Z Out 1.325 9.079 -
u2.sys_clk_cnt_5[8] Net - - - - 1
u2.sys_clk_cnt_8_.Q FD1S3BX D In 0.000 9.079 -
===============================================================================================
====================================
Detailed Report for Clock: System
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
-----------------------------------------------------------------------------------------------------
u4.no_bits_sent_0_.Q System FD1S3DX Q u4.no_bits_sent[0] 2.255 993.027
u5.no_bits_sent_0_.Q System FD1S3DX Q u5.no_bits_sent[0] 2.255 993.027
u4.no_bits_sent_1_.Q System FD1S3DX Q u4.no_bits_sent[1] 2.199 993.083
u5.no_bits_sent_1_.Q System FD1S3DX Q u5.no_bits_sent[1] 2.199 993.083
u3.no_bits_sent_0_.Q System FD1S3DX Q u3.no_bits_sent[0] 2.123 993.158
u6.no_bits_sent_0_.Q System FD1S3DX Q u6.no_bits_sent[0] 2.123 993.158
u3.no_bits_sent_1_.Q System FD1S3DX Q u3.no_bits_sent[1] 2.105 993.177
u6.no_bits_sent_1_.Q System FD1S3DX Q u6.no_bits_sent[1] 2.105 993.177
u3.no_bits_sent_2_.Q System FD1S3DX Q u3.no_bits_sent[2] 2.105 993.302
u3.no_bits_sent_3_.Q System FD1S3DX Q u3.no_bits_sent[3] 2.048 993.359
=====================================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
------------------------------------------------------------------------------------------------------
u4.no_bits_sent_0_.Q System FD1S3DX D u4.no_bits_sent_n0 999.676 993.027
u4.no_bits_sent_1_.Q System FD1S3DX D u4.no_bits_sent_n1 999.676 993.027
u4.no_bits_sent_2_.Q System FD1S3DX D u4.no_bits_sent_n2 999.676 993.027
u5.no_bits_sent_0_.Q System FD1S3DX D u5.no_bits_sent_n0 999.676 993.027
u5.no_bits_sent_1_.Q System FD1S3DX D u5.no_bits_sent_n1 999.676 993.027
u5.no_bits_sent_2_.Q System FD1S3DX D u5.no_bits_sent_n2 999.676 993.027
u3.no_bits_sent_0_.Q System FD1S3DX D u3.no_bits_sent_n0 999.676 993.158
u3.no_bits_sent_1_.Q System FD1S3DX D u3.no_bits_sent_n1 999.676 993.158
u3.no_bits_sent_2_.Q System FD1S3DX D u3.no_bits_sent_n2 999.676 993.158
u6.no_bits_sent_0_.Q System FD1S3DX D u6.no_bits_sent_n0 999.676 993.158
======================================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 1000.000
- Setup time: 0.324
= Required time: 999.676
- Propagation time: 6.649
= Slack (non-critical) : 993.027
Number of logic level(s): 3
Starting point: u4.no_bits_sent_0_.Q / Q
Ending point: u4.no_bits_sent_0_.Q / D
The start point is clocked by System [rising] on pin CK
The end point is clocked by System [rising] on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------
u4.no_bits_sent_0_.Q FD1S3DX Q Out 2.255 2.255 -
u4.no_bits_sent[0] Net - - - - 10
u4.no_bits_sent_c1 ORCALUT4 A In 0.000 2.255 -
u4.no_bits_sent_c1 ORCALUT4 Z Out 1.488 3.743 -
u4.no_bits_sent_c1 Net - - - - 2
u4.no_bits_sent17 ORCALUT4 D In 0.000 3.743 -
u4.no_bits_sent17 ORCALUT4 Z Out 1.582 5.325 -
u4.no_bits_sent17_i Net - - - - 3
u4.no_bits_sent_n0 ORCALUT4 A In 0.000 5.325 -
u4.no_bits_sent_n0 ORCALUT4 Z Out 1.325 6.649 -
u4.no_bits_sent_n0 Net - - - - 1
u4.no_bits_sent_0_.Q FD1S3DX D In 0.000 6.649 -
=======================================================================================
##### END OF TIMING REPORT #####]
Mapper successful!
Process took 0h:00m:07s realtime, 0h:00m:05s cputime
# Fri Jul 07 14:16:34 2006
###########################################################]
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