automake.err

一个UART的FPGA core

Synplicity VHDL/Verilog HDL Synthesizer finished successfully

#Build: Synplify for Lattice 8.4A, Build 429R, Dec  8 2005
#install: D:\ISPTOOLS5_1\SYNPBASE
#OS: Windows 2000 5.0
#Hostname: ALEXWU

#Fri Jul 07 14:16:24 2006

$ Start of Compile
#Fri Jul 07 14:16:24 2006

Synplicity Verilog Compiler, version 3.4.0, Build 070R, built Dec  5 2005
Copyright (C) 1994-2005, Synplicity Inc.  All Rights Reserved

@I::"D:\ISPTOOLS5_1\SYNPBASE\lib\lucent\machxo.v"
@I::"d:\ispTOOLS5_1\ispcpld\generic\verilog\synplify\generic.v"
@I::"d:\ispTOOLS5_1\ispcpld\..\cae_library\synthesis\verilog\machxo.v"
@I::"E:\yiluo\dd\uart.h"
@I::"E:\yiluo\dd\data_path.v"
@I::"E:\yiluo\dd\inter.v"
@I::"E:\yiluo\dd\dpram16x8.v"
@N: CG334 :"E:\yiluo\dd\dpram16x8.v":48:16:48:28|Read directive translate_off 
@N: CG333 :"E:\yiluo\dd\dpram16x8.v":50:16:50:27|Read directive translate_on 
@N: CG334 :"E:\yiluo\dd\dpram16x8.v":57:16:57:28|Read directive translate_off 
@N: CG333 :"E:\yiluo\dd\dpram16x8.v":59:16:59:27|Read directive translate_on 
@N: CG334 :"E:\yiluo\dd\dpram16x8.v":66:16:66:28|Read directive translate_off 
@N: CG333 :"E:\yiluo\dd\dpram16x8.v":68:16:68:27|Read directive translate_on 
@N: CG334 :"E:\yiluo\dd\dpram16x8.v":75:16:75:28|Read directive translate_off 
@N: CG333 :"E:\yiluo\dd\dpram16x8.v":77:16:77:27|Read directive translate_on 
@W: CS141 :"E:\yiluo\dd\dpram16x8.v":86:16:86:20|Unrecognized synthesis directive begin
@W: CS141 :"E:\yiluo\dd\dpram16x8.v":87:16:87:24|Unrecognized synthesis directive attribute
@W: CS141 :"E:\yiluo\dd\dpram16x8.v":88:16:88:24|Unrecognized synthesis directive attribute
@W: CS141 :"E:\yiluo\dd\dpram16x8.v":89:16:89:24|Unrecognized synthesis directive attribute
@W: CS141 :"E:\yiluo\dd\dpram16x8.v":90:16:90:24|Unrecognized synthesis directive attribute
@W: CS141 :"E:\yiluo\dd\dpram16x8.v":91:16:91:18|Unrecognized synthesis directive end
@I::"E:\yiluo\dd\uart_fifo.v"
@I::"E:\yiluo\dd\rcvr.v"
@I::"E:\yiluo\dd\txmit.v"
@I::"E:\yiluo\dd\baud1.v"
@I::"E:\yiluo\dd\decode.v"
@I::"E:\yiluo\dd\uart4_top.v"
Verilog syntax check successful!
Selecting top level module Uart4
@N: CG364 :"E:\yiluo\dd\decode.v":2:7:2:12|Synthesizing module decode

@W: CL159 :"E:\yiluo\dd\decode.v":12:13:12:16|Input data is unused
@N: CG364 :"E:\yiluo\dd\baud1.v":1:7:1:10|Synthesizing module baud

@N: CG364 :"d:\ispTOOLS5_1\ispcpld\..\cae_library\synthesis\verilog\machxo.v":185:7:185:10|Synthesizing module AND2

@N: CG364 :"d:\ispTOOLS5_1\ispcpld\..\cae_library\synthesis\verilog\machxo.v":337:7:337:13|Synthesizing module FD1P3DX

@N: CG364 :"d:\ispTOOLS5_1\ispcpld\..\cae_library\synthesis\verilog\machxo.v":107:7:107:14|Synthesizing module DPR16X2B

@N: CG364 :"E:\yiluo\dd\dpram16x8.v":8:7:8:15|Synthesizing module dpram16x8

@N: CG364 :"E:\yiluo\dd\uart_fifo.v":3:7:3:15|Synthesizing module UART_FIFO

@N: CG364 :"E:\yiluo\dd\txmit.v":3:7:3:11|Synthesizing module txmit

@W: CL159 :"E:\yiluo\dd\txmit.v":10:16:10:21|Input clk_in is unused
@N: CG364 :"E:\yiluo\dd\rcvr.v":3:7:3:10|Synthesizing module rcvr

@W: CL169 :"E:\yiluo\dd\rcvr.v":51:0:51:5|Pruning Register state1_4 

@N: CG364 :"E:\yiluo\dd\inter.v":2:8:2:12|Synthesizing module inter

@W: CL159 :"E:\yiluo\dd\inter.v":7:10:7:12|Input csn is unused
@W: CL159 :"E:\yiluo\dd\inter.v":7:14:7:15|Input we is unused
@W: CL159 :"E:\yiluo\dd\inter.v":8:12:8:15|Input addr is unused
@N: CG364 :"E:\yiluo\dd\data_path.v":2:7:2:15|Synthesizing module data_path

@N: CG364 :"E:\yiluo\dd\uart4_top.v":3:7:3:11|Synthesizing module Uart4

@W: CL156 :"E:\yiluo\dd\uart4_top.v":71:8:71:10|*Input csn to this expression [instance] has undriven bits which are being tied to 0 - a simulation mismatch is possible
@W: CL156 :"E:\yiluo\dd\uart4_top.v":71:8:71:10|*Input we to this expression [instance] has undriven bits which are being tied to 0 - a simulation mismatch is possible
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Jul 07 14:16:25 2006

###########################################################[
Version 8.4A
Synplicity Lattice ORCA FPGA Technology Mapper, Version 8.4.0.p, Build 020R, Built Jan  4 2006
Copyright (C) 1994-2005, Synplicity Inc.  All Rights Reserved
Setting fanout limit to 100
Starting Generic Flow
###########################################################[
Version 8.4A
Synplicity Generic Technology Mapper, Version 8.4.0.p, Build 020R, Built Jan  4 2006
Copyright (C) 1994-2005, Synplicity Inc.  All Rights Reserved
@N: MF249 |Running in 32-bit mode.
Reading Generic I/O pad type table from file <D:\ISPTOOLS5_1\SYNPBASE\lib/Generic/x_io_tbl.txt> 


Automatic dissolve at startup in view:work.UART_FIFO(verilog) of u0(dpram16x8)
Automatic dissolve at startup in view:work.txmit(verilog) of u0(UART_FIFO)
Automatic dissolve at startup in view:work.rcvr(verilog) of u1(UART_FIFO)
Automatic dissolve at startup in view:work.Uart4(verilog) of u12(inter)
RTL optimization done.

Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 37MB peak: 38MB)
@N:"e:\yiluo\dd\txmit.v":98:0:98:5|Found counter in view:work.txmit_u3(verilog) inst no_bits_sent[3:0]
@N:"e:\yiluo\dd\uart_fifo.v":36:0:36:5|Found counter in view:work.txmit_u3(verilog) inst u0.bottom[3:0]
@N:"e:\yiluo\dd\rcvr.v":89:0:89:5|Found counter in view:work.rcvr_u7(verilog) inst no_bits_rcvd[3:0]
@N:"e:\yiluo\dd\uart_fifo.v":36:0:36:5|Found counter in view:work.rcvr_u7(verilog) inst u1.bottom[3:0]
Automatic dissolve during optimization of view:work.Uart4(verilog) of u13(data_path)

Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 38MB peak: 39MB)
Reading Generic I/O pad type table from file <D:\ISPTOOLS5_1\SYNPBASE\lib/Generic/x_io_tbl.txt> 

Clock Buffers:
  Inserting Clock buffer on net baud_clk, 	TNM=baud_clk
  Inserting Clock buffer on net baud_clk1, 	TNM=baud_clk1


Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:01s; Memory used current: 39MB peak: 39MB)

Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:01s; Memory used current: 39MB peak: 39MB)

Finished preparing to map (Time elapsed 0h:00m:01s; Memory used current: 39MB peak: 39MB)
u3.un1_EF_1
we_en1
u3.u0.count[2]

u3.un1_EF_1
we_en1
u3.u0.count[1]

u3.u0.count_0_sqmuxa
u3.u0.top13
u3.u0.count[0]

u4.un1_EF_1
we_en2
u4.u0.count[2]

u4.un1_EF_1
we_en2
u4.u0.count[1]

u4.u0.count_0_sqmuxa
u4.u0.top13
u4.u0.count[0]

u5.un1_EF_1
we_en3
u5.u0.count[2]

u5.un1_EF_1
we_en3
u5.u0.count[1]

u5.u0.count_0_sqmuxa
u5.u0.top13
u5.u0.count[0]

u6.un1_EF_1
we_en4
u6.u0.count[2]

u6.un1_EF_1
we_en4
u6.u0.count[1]

u6.u0.count_0_sqmuxa
u6.u0.top13
u6.u0.count[0]

u7.pop
u7.wr
u7.u1.count[2]

u7.pop
u7.wr
u7.u1.count[1]

u7.u1.count_0_sqmuxa
u7.u1.top13
u7.u1.count[0]

u8.pop
u8.wr
u8.u1.count[2]

u8.pop
u8.wr
u8.u1.count[1]

u8.u1.count_0_sqmuxa
u8.u1.top13
u8.u1.count[0]

u9.pop
u9.wr
u9.u1.count[2]

u9.pop
u9.wr
u9.u1.count[1]

u9.u1.count_0_sqmuxa
u9.u1.top13
u9.u1.count[0]

u10.pop
u10.wr
u10.u1.count[2]

u10.pop
u10.wr
u10.u1.count[1]

u10.u1.count_0_sqmuxa
u10.u1.top13
u10.u1.count[0]

u3.un1_EF_1
we_en1
u3.u0.count[3]

u4.un1_EF_1
we_en2
u4.u0.count[3]

u5.un1_EF_1
we_en3
u5.u0.count[3]