decode.naf

一个UART的FPGA core

clk  i
addr[4]  i
addr[3]  i
addr[2]  i
addr[1]  i
addr[0]  i
data[7]  i
data[6]  i
data[5]  i
data[4]  i
data[3]  i
data[2]  i
data[1]  i
data[0]  i
cs_n  i
we_n  i
oe_n  i
baud_cs0  o
baud_cs1  o
baud_cs2  o
baud_cs3  o
fifot0_cs  o
fifot1_cs  o
fifot2_cs  o
fifot3_cs  o
fifor0_cs  o
fifor1_cs  o
fifor2_cs  o
fifor3_cs  o
inter_pos0  o
inter_pos1  o
inter_pos2  o
inter_pos3  o
inter_pos4  o
inter_pos5  o
inter_pos6  o
inter_pos7  o
inter_mask  o