uart.jid

一个UART的FPGA core

. Uart4 uart4_top.v e:\yiluo\dd\uart4_top.v
u6.u0 UART_FIFO uart_fifo.v e:\yiluo\dd\uart_fifo.v
u9.u1 UART_FIFO uart_fifo.v e:\yiluo\dd\uart_fifo.v
u8.u1 UART_FIFO uart_fifo.v e:\yiluo\dd\uart_fifo.v
u7.u1 UART_FIFO uart_fifo.v e:\yiluo\dd\uart_fifo.v
u5.u0 UART_FIFO uart_fifo.v e:\yiluo\dd\uart_fifo.v
u4.u0 UART_FIFO uart_fifo.v e:\yiluo\dd\uart_fifo.v
u9 rcvr rcvr.v e:\yiluo\dd\rcvr.v
u8 rcvr rcvr.v e:\yiluo\dd\rcvr.v
u7 rcvr rcvr.v e:\yiluo\dd\rcvr.v
u6 txmit txmit.v e:\yiluo\dd\txmit.v
u5 txmit txmit.v e:\yiluo\dd\txmit.v
u4 txmit txmit.v e:\yiluo\dd\txmit.v
u3 txmit txmit.v e:\yiluo\dd\txmit.v
u3.u0 UART_FIFO uart_fifo.v e:\yiluo\dd\uart_fifo.v
u2 baud baud1.v e:\yiluo\dd\baud1.v
u1 decode decode.v e:\yiluo\dd\decode.v
u6.u0.u0 dpram16x8 dpram16x8.v e:\yiluo\dd\dpram16x8.v
u9.u1.u0 dpram16x8 dpram16x8.v e:\yiluo\dd\dpram16x8.v
u8.u1.u0 dpram16x8 dpram16x8.v e:\yiluo\dd\dpram16x8.v
u7.u1.u0 dpram16x8 dpram16x8.v e:\yiluo\dd\dpram16x8.v
u5.u0.u0 dpram16x8 dpram16x8.v e:\yiluo\dd\dpram16x8.v
u4.u0.u0 dpram16x8 dpram16x8.v e:\yiluo\dd\dpram16x8.v
u3.u0.u0 dpram16x8 dpram16x8.v e:\yiluo\dd\dpram16x8.v
u10 rcvr rcvr.v e:\yiluo\dd\rcvr.v
u12 inter inter.v e:\yiluo\dd\inter.v
u13 data_path data_path.v e:\yiluo\dd\data_path.v
u10.u1.u0 dpram16x8 dpram16x8.v e:\yiluo\dd\dpram16x8.v
u10.u1 UART_FIFO uart_fifo.v e:\yiluo\dd\uart_fifo.v