baud1.v

来自「一个UART的FPGA core」· Verilog 代码 · 共 24 行

module baud(clk_in,rst,baud_clk,baud_clk1);

input clk_in;  //3.6864MHz
input rst;
output baud_clk,baud_clk1;

reg [8:0] sys_clk_cnt;//调整它就可以根据不同输入频率选baudrate

////////////////////////////Clock generator //////

always @(posedge clk_in or posedge rst) 
   if (rst)
      sys_clk_cnt <= 9'b100000000;
   else
      if (sys_clk_cnt == 9'd383)
         sys_clk_cnt <= 9'd0;
      else   
         sys_clk_cnt <= sys_clk_cnt + 1;
            
assign baud_clk = (sys_clk_cnt < 9'd192) ? 1'b1:1'b0;
assign baud_clk1 = ( (sys_clk_cnt > 9'd 96 ) & (sys_clk_cnt < 9'd 288 )) ? 1'b1:1'b0;

endmodule