📄 artx_config.lst
字号:
000001EC m_stk:
000001EC DS 2412
00000B58 os_active_TCB:
00000B58 DS 40
00000B80 os_tsk_robin:
00000B80 DS 4
00000B84 task_id:
00000B84 DS 4
00000B88 os_robin_time:
00000B88 DS 2
00000B8A os_del_flag:
00000B8A DS 1
*** CODE SEGMENT '?PR?os_idle_demon?T?ARTX_Config':
214: for (;;) {
00000000 L_4:
216: _idle_();//PWM
00000000 2101 MOV R1,#0x1
00000002 4800 LDR R0,=0xE01FC0C0
00000004 7001 STRB R1,[R0,#0x0]
217: }
00000006 E7FB B L_4 ; T=0x00000000
218: } /* end of os_idle_demon */
00000008 ENDP ; 'os_idle_demon?T'
*** CODE SEGMENT '?PR?os_tmr_call?T?ARTX_Config':
228: } /* end of os_tmr_call */
00000000 4770 BX R14
00000002 ENDP ; 'os_tmr_call?T'
*** CODE SEGMENT '?PR?os_stk_overflow?T?ARTX_Config':
233: static void os_stk_overflow (void) {
00000000 B500 PUSH {LR}
241: task_id = os_get_TID (os_runtask);
00000002 4800 LDR R0,=os_runtask ; os_runtask
00000004 6800 LDR R0,[R0,#0x0] ; os_runtask
00000006 F7FF BL os_get_TID?T ; T=0x0001 (1)
00000008 FFFB BL os_get_TID?T ; T=0x0001 (2)
0000000A 4800 LDR R1,=task_id ; task_id
0000000C 6008 STR R0,[R1,#0x0] ; task_id
244: for (;;);
0000000E L_8:
0000000E E7FE B L_8 ; T=0x0000000E
ARM COMPILER V2.42, ARTX_Config 20/01/06 15:26:03 PAGE 12
245: }
00000010 BC08 POP {R3}
00000012 4718 BX R3
00000014 ENDP ; 'os_stk_overflow?T'
*** CODE SEGMENT '?PR?os_clock_interrupt?A?ARTX_Config':
253: STMDB SP!,{R0-R1} ; Save Full Context
00000000 E92D0003 STMDB R13!,{R0-R1}
254: STMDB SP,{SP}^ ; User SP
00000004 E94D2000 STMDB R13,{SP}^
255: LDMDB SP,{R0}
00000008 E91D0001 LDMDB R13,{R0}
256: MRS R1,SPSR ; User CPSR
0000000C E14F1000 MRS R1,SPSR
257: SUB LR,LR,#0x4
00000010 E24EE004 SUB R14,R14,#0x0004
258: STMDB R0!,{R1,LR} ; Push PC, CPSR
00000014 E9204002 STMDB R0!,{R1,LR}
259: STMDB R0,{LR}^ ; Push User LR
00000018 E9404000 STMDB R0,{LR}^
260: SUB R0,R0,#0x4 ; Write back problem !!
0000001C E2400004 SUB R0,R0,#0x0004
261: STMDB R0!,{R2-R12} ; Push R12-R2
00000020 E9201FFC STMDB R0!,{R2-R12}
262: LDMIA SP!,{R2-R3}
00000024 E8BD000C LDMIA R13!,{R2-R3}
263: STMDB R0!,{R2-R3} ; Push R1-R0
00000028 E920000C STMDB R0!,{R2-R3}
265: LDR R1,=os_runtask ; os_runtask
0000002C E51F1000 LDR R1,=os_runtask
266: LDR R1,[R1,#0x0] ; os_runtask
00000030 E5911000 LDR R1,[R1,#0x0]
267: STR R0,[R1,#TCB_TSTACK] ; os_runtask->tsk_stack
00000034 E5810024 STR R0,[R1,#0x24]
269: OS_TIACK();
00000038 E3A01001 MOV R1,#0x1
0000003C E5100000 LDR R0,=0xE0008000
00000040 E5801000 STR R1,[R0,#0x0]
00000044 E3A01020 MOV R1,#0x20
00000048 E5100000 LDR R0,=0xFFFFF01C
0000004C E5801000 STR R1,[R0,#0x0]
00000050 E3A01000 MOV R1,#0x0
00000054 E5100000 LDR R0,=0xFFFFF030
00000058 E5801000 STR R1,[R0,#0x0]
270: tsk_lock ();
0000005C EBFFFFE7 BL tsk_lock?A ; Targ=0x0
271: os_runtask->full_ctx = __TRUE;
00000060 E3A00001 MOV R0,#0x1
00000064 E5101000 LDR R1,=os_runtask ; os_runtask
00000068 E5911000 LDR R1,[R1,#0x0] ; os_runtask
0000006C E5C10021 STRB R0,[R1,#0x21]
272: os_runtask->state = READY;
00000070 E3A00001 MOV R0,#0x1
00000074 E5101000 LDR R1,=os_runtask ; os_runtask
00000078 E5911000 LDR R1,[R1,#0x0] ; os_runtask
0000007C E5C10001 STRB R0,[R1,#0x1]
273: os_put_rdy_first (os_runtask);
00000080 E5100000 LDR R0,=os_runtask ; os_runtask
00000084 E5900000 LDR R0,[R0,#0x0] ; os_runtask
00000088 EBFFFFDC BL os_put_rdy_first?A ; Targ=0x0
274: os_runtask = &os_clock_TCB;
0000008C E5101000 LDR R1,=os_clock_TCB ; os_clock_TCB
00000090 E5100000 LDR R0,=os_runtask ; os_runtask
00000094 E5801000 STR R1,[R0,#0x0] ; os_runtask
275: os_clock_TCB.state = RUNNING;
00000098 E3A01002 MOV R1,#0x2
0000009C E5100000 LDR R0,=os_clock_TCB + 0x1 ; os_clock_TCB+1
ARM COMPILER V2.42, ARTX_Config 20/01/06 15:26:03 PAGE 13
000000A0 E5C01000 STRB R1,[R0,#0x0] ; os_clock_TCB+1
277: LDR R0,=os_runtask ; os_runtask
000000A4 E51F0000 LDR R0,=os_runtask
278: LDR R0,[R0,#0x0] ; os_runtask
000000A8 E5900000 LDR R0,[R0,#0x0]
279: LDR R0,[R0,#TCB_TSTACK] ; os_runtask->tsk_stack
000000AC E5900024 LDR R0,[R0,#0x24]
281: LDMIA R0!,{R4-R8,R12}
000000B0 E8B011F0 LDMIA R0!,{R4-R8,R12}
282: MSR SPSR_cxsf,R8
000000B4 E16FF008 MSR SPSR_cxsf,R8
283: STMDB SP,{R0} ; Set User SP
000000B8 E90D0001 STMDB R13,{R0}
284: LDMDB SP,{SP}^
000000BC E95D2000 LDMDB R13,{SP}^
285: MOVS PC,R12 ; RETI
000000C0 E1B0F00C MOVS R15,R12
287: } /* end of os_clock_interrupt */
000000C4 ENDP ; 'os_clock_interrupt?A'
*** CODE SEGMENT '?PR?os_def_interrupt?A?ARTX_Config':
291: void os_def_interrupt (void) __irq {
00000000 E92D0003 STMDB R13!,{R0-R1}
293: OS_IACK();
00000004 E3A01000 MOV R1,#0x0
00000008 E5100000 LDR R0,=0xFFFFF030
0000000C E5801000 STR R1,[R0,#0x0]
294: }
00000010 E8BD0003 LDMIA R13!,{R0-R1}
00000014 E25EF004 SUBS R15,R14,#0x0004
00000018 ENDP ; 'os_def_interrupt?A'
*** CODE SEGMENT '?PR?os_tmr_init?T?ARTX_Config':
301: OS_TINIT();
00000000 4800 LDR R1,=0x249EF
00000002 4800 LDR R0,=0xE0008018
00000004 6001 STR R1,[R0,#0x0]
00000006 2103 MOV R1,#0x3
00000008 4800 LDR R0,=0xE0008014
0000000A 6001 STR R1,[R0,#0x0]
0000000C 2101 MOV R1,#0x1
0000000E 4800 LDR R0,=0xE0008004
00000010 6001 STR R1,[R0,#0x0]
00000012 4900 LDR R1,=os_def_interrupt?A ; os_def_interrupt?A
00000014 4800 LDR R0,=0xFFFFF034
00000016 6001 STR R1,[R0,#0x0]
00000018 4900 LDR R1,=os_clock_interrupt?A ; os_clock_interrupt?A
0000001A 4800 LDR R0,=0xFFFFF13C
0000001C 6001 STR R1,[R0,#0x0]
0000001E 2125 MOV R1,#0x25
00000020 4800 LDR R0,=0xFFFFF23C
00000022 6001 STR R1,[R0,#0x0]
303: os_robin_time = OS_ROBINTOUT;
00000024 2105 MOV R1,#0x5
00000026 4800 LDR R0,=os_robin_time ; os_robin_time
00000028 8001 STRH R1,[R0,#0x0] ; os_robin_time
305: } /* end of os_tmr_init */
0000002A 4770 BX R14
0000002C ENDP ; 'os_tmr_init?T'
*** CODE SEGMENT '?PR?os_tmr_reload?T?ARTX_Config':
312: } /* end of os_tmr_reload */
00000000 4770 BX R14
00000002 ENDP ; 'os_tmr_reload?T'
*** CODE SEGMENT '?PR?os_tmr_force_irq?T?ARTX_Config':
318: OS_TFIRQ();
00000000 2220 MOV R2,#0x20
00000002 4800 LDR R0,=0xFFFFF018
00000004 6801 LDR R1,[R0,#0x0]
ARM COMPILER V2.42, ARTX_Config 20/01/06 15:26:03 PAGE 14
00000006 4311 ORR R1,R2
00000008 6001 STR R1,[R0,#0x0]
319: } /* end of os_tmr_force_irq */
0000000A 4770 BX R14
0000000C ENDP ; 'os_tmr_force_irq?T'
*** CODE SEGMENT '?PR?os_tmr_inspect_cnt?T?ARTX_Config':
325: return (OS_TVAL);
00000000 4800 LDR R0,=0xE0008008
00000002 6800 LDR R0,[R0,#0x0]
326: } /* end of os_tmr_inspect_cnt */
00000004 4770 BX R14
00000006 ENDP ; 'os_tmr_inspect_cnt?T'
*** CODE SEGMENT '?PR?os_tmr_inspect_ovf?T?ARTX_Config':
332: return (OS_TOVF);
00000000 4800 LDR R0,=0xE0008000
00000002 6800 LDR R0,[R0,#0x0]
00000004 2101 MOV R1,#0x1
00000006 4008 AND R0,R1
333: } /* end of os_tmr_inspect_ovf */
00000008 4770 BX R14
0000000A ENDP ; 'os_tmr_inspect_ovf?T'
*** CODE SEGMENT '?PR?tsk_lock?T?ARTX_Config':
340: OS_LOCK();
00000000 2120 MOV R1,#0x20
00000002 4800 LDR R0,=0xFFFFF014
00000004 6001 STR R1,[R0,#0x0]
341: } /* end of tsk_lock */
00000006 4770 BX R14
00000008 ENDP ; 'tsk_lock?T'
*** CODE SEGMENT '?PR?tsk_unlock?T?ARTX_Config':
347: OS_UNLOCK();
00000000 2220 MOV R2,#0x20
00000002 4800 LDR R0,=0xFFFFF010
00000004 6801 LDR R1,[R0,#0x0]
00000006 4311 ORR R1,R2
00000008 6001 STR R1,[R0,#0x0]
348: } /* end of tsk_unlock */
0000000A 4770 BX R14
0000000C ENDP ; 'tsk_unlock?T'
*** CODE SEGMENT '?PR?os_init_mem?T?ARTX_Config':
352: void os_init_mem (void) {
00000000 B500 PUSH {LR}
00000002 ; SCOPE-START
355: for (i = 0; i < OS_TASKCNT; i++) {
00000002 2000 MOV R0,#0x0
00000004 ---- Variable 'i' assigned to Register 'R0' ----
00000004 L_16:
356: os_active_TCB[i] = NULL;
00000004 2100 MOV R1,#0x0
00000006 1C03 MOV R3,R0 ; i
00000008 009B LSL R3,R3,#0x2 ; i
0000000A 4800 LDR R2,=os_active_TCB ; os_active_TCB
0000000C 50D1 STR R1,[R2,R3]
357: }
0000000E 3001 ADD R0,#0x1
00000010 1C01 MOV R1,R0 ; i
00000012 290A CMP R1,#0xA ; i
00000014 D3F6 BCC L_16 ; T=0x00000004
358: _init_box (&m_tcb, sizeof(m_tcb), sizeof(struct OS_TCB));
00000016 4800 LDR R0,=m_tcb ; m_tcb
00000018 497B LDR R1,=0x1EC
0000001A 2230 MOV R2,#0x30
0000001C F7FF BL _init_box?T ; T=0x0001 (1)
0000001E FFF0 BL _init_box?T ; T=0x0001 (2)
359: _init_box (&m_stk, sizeof(m_stk), OS_STKSIZE*4);
00000020 4800 LDR R0,=m_stk ; m_stk
ARM COMPILER V2.42, ARTX_Config 20/01/06 15:26:03 PAGE 15
00000022 4800 LDR R1,=0x96C
00000024 22C8 MOV R2,#0xC8
00000026 F7FF BL _init_box?T ; T=0x0001 (1)
00000028 FFEB BL _init_box?T ; T=0x0001 (2)
0000002A ; SCOPE-END
363: } /* end of os_init_mem */
0000002A BC08 POP {R3}
0000002C 4718 BX R3
0000002E ENDP ; 'os_init_mem?T'
*** CODE SEGMENT '?PR?os_alloc_TCB?T?ARTX_Config':
367: P_TCB os_alloc_TCB () {
00000000 B500 PUSH {LR}
368: return (_alloc_box (m_tcb));
00000002 4800 LDR R0,=m_tcb ; m_tcb
00000004 DF06 SWI 0x6 ; _alloc_box?T
369: } /* end of os_alloc_TCB */
00000006 BC08 POP {R3}
00000008 4718 BX R3
0000000A ENDP ; 'os_alloc_TCB?T'
*** CODE SEGMENT '?PR?os_free_TCB?T?ARTX_Config':
373: void os_free_TCB (P_TCB p_TCB) {
00000000 B510 PUSH {R4,LR}
00000002 1C04 MOV R4,R0 ; p_TCB
00000004 ---- Variable 'p_TCB' assigned to Register 'R4' ----
375: _free_box (m_stk, p_TCB->stack);
00000004 1C20 MOV R0,R4 ; p_TCB
00000006 6A81 LDR R1,[R0,#0x28]
00000008 4800 LDR R0,=m_stk ; m_stk
0000000A DF07 SWI 0x7 ; _free_box?T
376: _free_box (m_tcb, p_TCB);
0000000C 4800 LDR R0,=m_tcb ; m_tcb
0000000E 1C21 MOV R1,R4 ; p_TCB
00000010 DF07 SWI 0x7 ; _free_box?T
378: if (os_runtask == p_TCB) {
00000012 1C21 MOV R1,R4 ; p_TCB
00000014 4800 LDR R0,=os_runtask ; os_runtask
00000016 6800 LDR R0,[R0,#0x0] ; os_runtask
00000018 4288 CMP R0,R1 ; p_TCB
0000001A D102 BNE L_19 ; T=0x00000022
380: os_del_flag = __TRUE;
0000001C 2101 MOV R1,#0x1
0000001E 4800 LDR R0,=os_del_flag ; os_del_flag
00000020 7001 STRB R1,[R0,#0x0] ; os_del_flag
381: }
00000022 L_19:
383: } /* end of os_free_TCB */
00000022 BC10 POP {R4}
00000024 BC08 POP {R3}
00000026 4718 BX R3
00000028 ENDP ; 'os_free_TCB?T'
*** CODE SEGMENT '?PR?os_alloc_TMR?T?ARTX_Config':
391: return (NULL);
00000000 2000 MOV R0,#0x0
393: } /* end of os_alloc_TMR */
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