auide.patch

patches for linux-2.6.

+}
+
+static int auide_dma_end(ide_drive_t *drive)
+{
+//      printk("begin %s\n", __FUNCTION__);
+        ide_hwif_t *hwif = HWIF(drive);
+        _auide_hwif *ahwif = (_auide_hwif*)hwif->hwif_data;
+
+        if (hwif->sg_nents) {
+                dma_unmap_sg(ahwif->dev, hwif->sg_table, hwif->sg_nents,
+                             hwif->sg_dma_direction);
+                hwif->sg_nents = 0;
+        }
+
+        return 0;
+}
+
+static void auide_dma_start(ide_drive_t *drive )
+{
+//      printk("%s\n", __FUNCTION__);
+}
+
+ide_startstop_t auide_dma_intr(ide_drive_t *drive)
+{
+        //printk("%s\n", __FUNCTION__);
+
+        u8 stat = 0, dma_stat = 0;
+
+        dma_stat = HWIF(drive)->ide_dma_end(drive);
+        stat = HWIF(drive)->INB(IDE_STATUS_REG);        /* get drive status */
+        if (OK_STAT(stat,DRIVE_READY,drive->bad_wstat|DRQ_STAT)) {
+                if (!dma_stat) {
+                        struct request *rq = HWGROUP(drive)->rq;
+
+                        DRIVER(drive)->end_request(drive, 1, rq->nr_sectors);
+                        return ide_stopped;
+                }
+                printk(KERN_ERR "%s: dma_intr: bad DMA status (dma_stat=%x)\n",
+                                 drive->name, dma_stat);
+        }
+        return ide_error(drive, "dma_intr", stat);
+}
+
+static void auide_dma_exec_cmd(ide_drive_t *drive, u8 command)
+{
+        //printk("%s\n", __FUNCTION__);
+
+        /* issue cmd to drive */
+        ide_execute_command(drive, command, &auide_dma_intr,
+                            (2*WAIT_CMD), NULL);
+}
+
+static int auide_dma_setup(ide_drive_t *drive)
+{
+//      printk("%s\n", __FUNCTION__);
+
+        if (drive->media != ide_disk)
+                return 1;
+
+        if (!auide_build_dmatable(drive))
+                        /* try PIO instead of DMA */
+                        return 1;
+
+        drive->waiting_for_dma = 1;
+
+        return 0;
+}
+
+static int auide_dma_check(ide_drive_t *drive)
+{
+//      printk("%s\n", __FUNCTION__);
+
+#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
+        if( !dbdma_init_done ){
+                auide_hwif.white_list = in_drive_list(drive->id,
+                                                      dma_white_list);
+                auide_hwif.black_list = in_drive_list(drive->id,
+                                                      dma_black_list);
+                auide_hwif.drive = drive;
+                auide_ddma_init(&auide_hwif);
+                dbdma_init_done = 1;
+        }
+#endif
+
+        /* Is the drive in our DMA black list? */
+        if ( auide_hwif.black_list ) {
+                drive->using_dma = 0;
+                printk("%s found in dma_blacklist[]! Disabling DMA.\n",
+                drive->id->model);
+        }
+        else
+                drive->using_dma = 1;
+
+        return HWIF(drive)->ide_dma_host_on(drive);
+}
+
+static int auide_dma_test_irq(ide_drive_t *drive)
+{
+//      printk("%s\n", __FUNCTION__);
+
+        if (!drive->waiting_for_dma)
+                printk(KERN_WARNING "%s: ide_dma_test_irq \
+                                     called while not waiting\n", drive->name);
+
+        /* If dbdma didn't execute the STOP command yet, the
+         * active bit is still set
+	 */
+        drive->waiting_for_dma++;
+        if (drive->waiting_for_dma >= DMA_WAIT_TIMEOUT) {
+                printk(KERN_WARNING "%s: timeout waiting for ddma to \
+                                     complete\n", drive->name);
+                return 1;
+        }
+        udelay(10);
+        return 0;
+}
+
+static int auide_dma_host_on(ide_drive_t *drive)
+{
+//      printk("%s\n", __FUNCTION__);
+        return 0;
+}
+
+static int auide_dma_on(ide_drive_t *drive)
+{
+//      printk("%s\n", __FUNCTION__);
+        drive->using_dma = 1;
+        return auide_dma_host_on(drive);
+}
+
+
+static int auide_dma_host_off(ide_drive_t *drive)
+{
+//      printk("%s\n", __FUNCTION__);
+        return 0;
+}
+
+static int auide_dma_off_quietly(ide_drive_t *drive)
+{
+//      printk("%s\n", __FUNCTION__);
+        drive->using_dma = 0;
+        return auide_dma_host_off(drive);
+}
+
+static int auide_dma_lostirq(ide_drive_t *drive)
+{
+//      printk("%s\n", __FUNCTION__);
+
+        printk(KERN_ERR "%s: IRQ lost\n", drive->name);
+        return 0;
+}
+
+static void auide_ddma_tx_callback(int irq, void *param, struct pt_regs *regs)
+{
+//      printk("%s\n", __FUNCTION__);
+
+        _auide_hwif *ahwif = (_auide_hwif*)param;
+        ahwif->drive->waiting_for_dma = 0;
+        return;
+}
+
+static void auide_ddma_rx_callback(int irq, void *param, struct pt_regs *regs)
+{
+//      printk("%s\n", __FUNCTION__);
+
+        _auide_hwif *ahwif = (_auide_hwif*)param;
+        ahwif->drive->waiting_for_dma = 0;
+        return;
+}
+
+static int auide_dma_timeout(ide_drive_t *drive)
+{
+//      printk("%s\n", __FUNCTION__);
+
+        printk(KERN_ERR "%s: DMA timeout occurred: ", drive->name);
+
+        if (HWIF(drive)->ide_dma_test_irq(drive))
+                return 0;
+
+        return HWIF(drive)->ide_dma_end(drive);
+}
+#endif /* end CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */
+
+
+static int auide_ddma_init( _auide_hwif *auide )
+{
+//      printk("%s\n", __FUNCTION__);
+
+        dbdev_tab_t source_dev_tab;
+#if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
+        dbdev_tab_t target_dev_tab;
+        ide_hwif_t *hwif = auide->hwif;
+        char warning_output [2][80];
+        int i;
+#endif
+
+        /* Add our custom device to DDMA device table */
+        /* Create our new device entries in the table */
+#if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
+        source_dev_tab.dev_id = AU1XXX_ATA_DDMA_REQ;
+
+        if( auide->white_list || auide->black_list ){
+                source_dev_tab.dev_tsize       = 8;
+                source_dev_tab.dev_devwidth    = 32;
+                source_dev_tab.dev_physaddr    = (u32)AU1XXX_ATA_PHYS_ADDR;
+                source_dev_tab.dev_intlevel    = 0;
+                source_dev_tab.dev_intpolarity = 0;
+
+                /* init device table for target - static bus controller - */
+                target_dev_tab.dev_id          = DSCR_CMD0_ALWAYS;
+                target_dev_tab.dev_tsize       = 8;
+                target_dev_tab.dev_devwidth    = 32;
+                target_dev_tab.dev_physaddr    = (u32)AU1XXX_ATA_PHYS_ADDR;
+                target_dev_tab.dev_intlevel    = 0;
+                target_dev_tab.dev_intpolarity = 0;
+                target_dev_tab.dev_flags       = DEV_FLAGS_ANYUSE;
+        }
+        else{
+                source_dev_tab.dev_tsize       = 1;
+                source_dev_tab.dev_devwidth    = 16;
+                source_dev_tab.dev_physaddr    = (u32)AU1XXX_ATA_PHYS_ADDR;
+                source_dev_tab.dev_intlevel    = 0;
+                source_dev_tab.dev_intpolarity = 0;
+
+                /* init device table for target - static bus controller - */
+                target_dev_tab.dev_id          = DSCR_CMD0_ALWAYS;
+                target_dev_tab.dev_tsize       = 1;
+                target_dev_tab.dev_devwidth    = 16;
+                target_dev_tab.dev_physaddr    = (u32)AU1XXX_ATA_PHYS_ADDR;
+                target_dev_tab.dev_intlevel    = 0;
+                target_dev_tab.dev_intpolarity = 0;
+                target_dev_tab.dev_flags       = DEV_FLAGS_ANYUSE;
+
+                sprintf(&warning_output[0][0],
+                        "%s is not on ide driver white list.",
+                        auide_hwif.drive->id->model);
+                for ( i=strlen(&warning_output[0][0]) ; i<76; i++ ){
+                        sprintf(&warning_output[0][i]," ");
+                }
+
+                sprintf(&warning_output[1][0],
+                "To add %s please read 'Documentation/mips/AU1xxx_IDE.README'.",
+                        auide_hwif.drive->id->model);
+                for ( i=strlen(&warning_output[1][0]) ; i<76; i++ ){
+                        sprintf(&warning_output[1][i]," ");
+                }
+
+                printk("\n****************************************");
+                printk("****************************************\n");
+                printk("* %s *\n",&warning_output[0][0]);
+                printk("* Switch to safe MWDMA Mode!            ");
+                printk("                                       *\n");
+                printk("* %s *\n",&warning_output[1][0]);
+                printk("****************************************");
+                printk("****************************************\n\n");        
+        }
+#else
+        source_dev_tab.dev_id = DSCR_CMD0_ALWAYS;
+        source_dev_tab.dev_tsize       = 8;
+        source_dev_tab.dev_devwidth    = 32;
+        source_dev_tab.dev_physaddr    = (u32)AU1XXX_ATA_PHYS_ADDR;
+        source_dev_tab.dev_intlevel    = 0;
+        source_dev_tab.dev_intpolarity = 0;
+#endif
+
+#if CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON
+        /* set flags for tx channel */
+        source_dev_tab.dev_flags =  DEV_FLAGS_OUT
+                                  | DEV_FLAGS_SYNC
+                                  | DEV_FLAGS_BURSTABLE;
+        auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
+        /* set flags for rx channel */
+        source_dev_tab.dev_flags =  DEV_FLAGS_IN
+                                  | DEV_FLAGS_SYNC
+                                  | DEV_FLAGS_BURSTABLE;
+        auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
+#else
+        /* set flags for tx channel */
+        source_dev_tab.dev_flags = DEV_FLAGS_OUT | DEV_FLAGS_SYNC;
+        auide->tx_dev_id         = au1xxx_ddma_add_device( &source_dev_tab );
+        /* set flags for rx channel */
+        source_dev_tab.dev_flags = DEV_FLAGS_IN | DEV_FLAGS_SYNC;
+        auide->rx_dev_id         = au1xxx_ddma_add_device( &source_dev_tab );
+#endif
+
+#if  defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
+
+        auide->target_dev_id           = au1xxx_ddma_add_device(&target_dev_tab);
+
+        /* Get a channel for TX */
+        auide->tx_chan = au1xxx_dbdma_chan_alloc(auide->target_dev_id,
+                                                 auide->tx_dev_id,
+                                                 auide_ddma_tx_callback,
+                                                 (void*)auide);
+        /* Get a channel for RX */
+        auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
+                                                 auide->target_dev_id, 
+                                                 auide_ddma_rx_callback, 
+                                                 (void*)auide);
+#else   /* CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA */
+        /*
+         * Note: if call back is not enabled, update ctp->cur_ptr manually 
+         */
+        auide->tx_chan = au1xxx_dbdma_chan_alloc(DSCR_CMD0_ALWAYS,
+                                                 auide->tx_dev_id,
+                                                 NULL, 
+                                                 (void*)auide);
+        auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
+                                                 DSCR_CMD0_ALWAYS,
+                                                 NULL,
+                                                 (void*)auide);
+#endif
+        auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan, 
+                                                             NUM_DESCRIPTORS);
+        auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan, 
+                                                             NUM_DESCRIPTORS);
+
+#if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
+        hwif->dmatable_cpu = dma_alloc_coherent(auide->dev,
+                                                PRD_ENTRIES * PRD_BYTES,        /* 1 Page */
+                                                &hwif->dmatable_dma, GFP_KERNEL);
+
+        auide->sg_table = kmalloc(sizeof(struct scatterlist) * PRD_ENTRIES,
+                                GFP_KERNEL|GFP_DMA);
+        if (auide->sg_table == NULL) {
+                return -ENOMEM;
+        }
+#endif
+        au1xxx_dbdma_start( auide->tx_chan );
+        au1xxx_dbdma_start( auide->rx_chan );
+        return 0;
+}
+
+static void auide_setup_ports(hw_regs_t *hw)
+{
+//      printk("%s\n", __FUNCTION__);
+
+        int i;
+#define ide_ioreg_t unsigned long
+        ide_ioreg_t *ata_regs = hw->io_ports;
+
+        for (i = 0; i < IDE_CONTROL_OFFSET; i++) {
+                *ata_regs++ = (ide_ioreg_t) auide_base 
+                            + (ide_ioreg_t)(i << AU1XXX_ATA_REG_OFFSET);
+        }
+
+        /* set the Alternative Status register */
+        *ata_regs = (ide_ioreg_t) auide_base 
+                  + (ide_ioreg_t)(14 << AU1XXX_ATA_REG_OFFSET);
+}
+
+int __init auide_probe(void)
+{
+//      printk("%s\n", __FUNCTION__);
+