📄 fs4534.patch
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diff -Naur linux26-cvs/arch/mips/au1000/common/gpio.c linux26-fs4553/arch/mips/au1000/common/gpio.c--- linux26-cvs/arch/mips/au1000/common/gpio.c 1969-12-31 18:00:00.000000000 -0600+++ linux26-fs4553/arch/mips/au1000/common/gpio.c 2005-08-09 14:40:27.000000000 -0500@@ -0,0 +1,118 @@+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <asm/mach-au1x00/au1000.h>
+#include <asm/mach-au1x00/au1xxx_gpio.h>
+
+#define gpio1 sys
+#if !defined(CONFIG_SOC_AU1000)
+static AU1X00_GPIO2 * const gpio2 = (AU1X00_GPIO2 *)GPIO2_BASE;
+
+#define GPIO2_OUTPUT_ENABLE_MASK 0x00010000
+
+int au1xxx_gpio2_read(int signal)
+{
+ signal -= 200;
+/* gpio2->dir &= ~(0x01 << signal); //Set GPIO to input */
+ return ((gpio2->pinstate >> signal) & 0x01);
+}
+
+void au1xxx_gpio2_write(int signal, int value)
+{
+ signal -= 200;
+
+ gpio2->output = (GPIO2_OUTPUT_ENABLE_MASK << signal) |
+ (value << signal);
+}
+
+void au1xxx_gpio2_tristate(int signal)
+{
+ signal -= 200;
+ gpio2->dir &= ~(0x01 << signal); /* Set GPIO to input */
+}
+#endif
+
+int au1xxx_gpio1_read(int signal)
+{
+/* gpio1->trioutclr |= (0x01 << signal); */
+ return ((gpio1->pinstaterd >> signal) & 0x01);
+}
+
+void au1xxx_gpio1_write(int signal, int value)
+{
+ if(value)
+ gpio1->outputset = (0x01 << signal);
+ else
+ gpio1->outputclr = (0x01 << signal); /* Output a Zero */
+}
+
+void au1xxx_gpio1_tristate(int signal)
+{
+ gpio1->trioutclr = (0x01 << signal); /* Tristate signal */
+}
+
+
+int au1xxx_gpio_read(int signal)
+{
+ if(signal >= 200)
+#if defined(CONFIG_SOC_AU1000)
+ return 0;
+#else
+ return au1xxx_gpio2_read(signal);
+#endif
+ else
+ return au1xxx_gpio1_read(signal);
+}
+
+void au1xxx_gpio_write(int signal, int value)
+{
+ if(signal >= 200)
+#if defined(CONFIG_SOC_AU1000)
+ ;
+#else
+ au1xxx_gpio2_write(signal, value);
+#endif
+ else
+ au1xxx_gpio1_write(signal, value);
+}
+
+void au1xxx_gpio_tristate(int signal)
+{
+ if(signal >= 200)
+#if defined(CONFIG_SOC_AU1000)
+ ;
+#else
+ au1xxx_gpio2_tristate(signal);
+#endif
+ else
+ au1xxx_gpio1_tristate(signal);
+}
+
+void au1xxx_gpio1_set_inputs(void)
+{
+ gpio1->pininputen = 0;
+}
+
+EXPORT_SYMBOL(au1xxx_gpio1_set_inputs);
+EXPORT_SYMBOL(au1xxx_gpio_tristate);
+EXPORT_SYMBOL(au1xxx_gpio_write);
+EXPORT_SYMBOL(au1xxx_gpio_read);
diff -Naur linux26-cvs/arch/mips/au1000/common/Makefile linux26-fs4553/arch/mips/au1000/common/Makefile--- linux26-cvs/arch/mips/au1000/common/Makefile 2005-08-12 13:38:57.000000000 -0500+++ linux26-fs4553/arch/mips/au1000/common/Makefile 2005-08-09 14:40:27.000000000 -0500@@ -8,7 +8,7 @@ obj-y += prom.o int-handler.o irq.o puts.o time.o reset.o \ au1xxx_irqmap.o clocks.o platform.o power.o setup.o \- sleeper.o cputable.o dma.o dbdma.o+ sleeper.o cputable.o dma.o dbdma.o gpio.o obj-$(CONFIG_AU1X00_USB_DEVICE) += usbdev.o obj-$(CONFIG_KGDB) += dbg_io.odiff -Naur linux26-cvs/drivers/mmc/au1xmmc.c linux26-fs4553/drivers/mmc/au1xmmc.cdiff -Naur linux26-cvs/drivers/video/au1200fb.c linux26-fs4553/drivers/video/au1200fb.c--- linux26-cvs/drivers/video/au1200fb.c 2005-08-12 13:39:21.741347472 -0500+++ linux26-fs4553/drivers/video/au1200fb.c 2005-08-12 08:29:20.000000000 -0500@@ -325,7 +325,7 @@ struct panel_settings {- const char name[25]; /* Full name <vendor>_<model> */+ const char name[64]; /* Full name <vendor>_<model> */ struct fb_monspecs monspecs; /* FB monitor specs */ @@ -638,9 +638,97 @@ 856, 856, 480, 480, },- #if defined(CONFIG_FOCUS_ENHANCEMENTS)- /* FIX!!!! */+ [9] = { /* Index 9: Focus FS453 TV-Out 640x480 */+ .name = "FS453_640x480 (Composite/S-Video)",+ .monspecs = {+ .modedb = NULL,+ .modedb_len = 0,+ .hfmin = 30000, // FIX+ .hfmax = 70000, // FIX+ .vfmin = 60, // FIX+ .vfmax = 60, // FIX+ .dclkmin = 6000000, // FIX+ .dclkmax = 28000000, // FIX+ .input = FB_DISP_RGB,+ },+ .mode_screen = LCD_SCREEN_SX_N(640) | LCD_SCREEN_SY_N(480),+ .mode_horztiming = LCD_HORZTIMING_HND2_N(143) | LCD_HORZTIMING_HND1_N(143) | LCD_HORZTIMING_HPW_N(10),+ .mode_verttiming = LCD_VERTTIMING_VND2_N(30) | LCD_VERTTIMING_VND1_N(30) | LCD_VERTTIMING_VPW_N(5),+ .mode_clkcontrol = 0x00480000 | (1<<17) | (1<<18), /* External Clock, 1:1 clock ratio */+ .mode_pwmdiv = 0x00000000,+ .mode_pwmhi = 0x00000000,+ .mode_outmask = 0x00FFFFFF,+ .mode_fifoctrl = 0x2f2f2f2f,+ .mode_toyclksrc = 0x00000000,+ .mode_backlight = 0x00000000,+ .mode_auxpll = 8, /* 96MHz AUXPLL */+ .device_init = board_au1200fb_focus_init_cvsv,+ .device_shutdown = board_au1200fb_focus_shutdown,+ 640, 640,+ 480, 480,+ },+ + [10] = { /* Index 10: Focus FS453 TV-Out 640x480 */+ "FS453_640x480 (Component Video)",+ .monspecs = {+ .modedb = NULL,+ .modedb_len = 0,+ .hfmin = 30000, // FIX+ .hfmax = 70000, // FIX+ .vfmin = 60, // FIX+ .vfmax = 60, // FIX+ .dclkmin = 6000000, // FIX+ .dclkmax = 28000000, // FIX+ .input = FB_DISP_RGB,+ },+ .mode_screen = LCD_SCREEN_SX_N(640) | LCD_SCREEN_SY_N(480),+ .mode_horztiming = LCD_HORZTIMING_HND2_N(143) | LCD_HORZTIMING_HND1_N(143) | LCD_HORZTIMING_HPW_N(10),+ .mode_verttiming = LCD_VERTTIMING_VND2_N(30) | LCD_VERTTIMING_VND1_N(30) | LCD_VERTTIMING_VPW_N(5),+ .mode_clkcontrol = 0x00480000 | (1<<17) | (1<<18), /* External Clock, 1:1 clock ratio */+ .mode_pwmdiv = 0x00000000,+ .mode_pwmhi = 0x00000000,+ .mode_outmask = 0x00FFFFFF,+ .mode_fifoctrl = 0x2f2f2f2f,+ .mode_toyclksrc = 0x00000000,+ .mode_backlight = 0x00000000,+ .mode_auxpll = 8, /* 96MHz AUXPLL */+ .device_init = board_au1200fb_focus_init_component,+ .device_shutdown = board_au1200fb_focus_shutdown,+ 640, 640,+ 480, 480,+ }, + + [11] = { /* Index 11: Focus FS453 TV-Out 640x480 */+ "FS453_640x480 (HDTV)",+ .monspecs = {+ .modedb = NULL,+ .modedb_len = 0,+ .hfmin = 30000, // FIX+ .hfmax = 70000, // FIX+ .vfmin = 60, // FIX+ .vfmax = 60, // FIX+ .dclkmin = 6000000, // FIX+ .dclkmax = 28000000, // FIX+ .input = FB_DISP_RGB,+ },+ .mode_screen = LCD_SCREEN_SX_N(720) | LCD_SCREEN_SY_N(480),+ .mode_horztiming = LCD_HORZTIMING_HND2_N(28) | LCD_HORZTIMING_HND1_N(46) | LCD_HORZTIMING_HPW_N(64),+ .mode_verttiming = LCD_VERTTIMING_VND2_N(7) | LCD_VERTTIMING_VND1_N(31) | LCD_VERTTIMING_VPW_N(7),+ .mode_clkcontrol = 0x00480000 | (1<<17) | (1<<18), /* External Clock, 1:1 clock ratio */+ .mode_pwmdiv = 0x00000000,+ .mode_pwmhi = 0x00000000,+ .mode_outmask = 0x00FFFFFF,+ .mode_fifoctrl = 0x2f2f2f2f,+ .mode_toyclksrc = 0x00000000,+ .mode_backlight = 0x00000000,+ .mode_auxpll = 8, /* 96MHz AUXPLL */+ .device_init = board_au1200fb_focus_init_hdtv,+ .device_shutdown = board_au1200fb_focus_shutdown,+ 640, 640,+ 480, 480,++ }, #endif }; diff -Naur linux26-cvs/drivers/video/focus/focus.c linux26-fs4553/drivers/video/focus/focus.c--- linux26-cvs/drivers/video/focus/focus.c 1969-12-31 18:00:00.000000000 -0600+++ linux26-fs4553/drivers/video/focus/focus.c 2005-08-09 14:40:13.000000000 -0500@@ -0,0 +1,147 @@+#include "os.h"
+#include "focus.h"
+#include "sio.h"
+#include "sioll.h"
+
+static uint32 focus_read(FOCUS_REGISTER_ID id)
+{
+ unsigned long data;
+ SIO_read(FS453_ADDRESS, focus_registers[id].address, &data, focus_registers[id].size);
+ return (uint32) data;
+}
+
+static void focus_write(FOCUS_REGISTER_ID id, uint32 value)
+{
+ SIO_write(FS453_ADDRESS, focus_registers[id].address, (unsigned long) value, focus_registers[id].size);
+}
+
+static void focus_set_bits(FOCUS_REGISTER_ID id, uint32 bits)
+{
+ focus_write(id, focus_read(id) | bits);
+}
+
+static void focus_clear_bits(FOCUS_REGISTER_ID id, uint32 bits)
+{
+ focus_write(id, focus_read(id) & ~bits);
+}
+
+void focus_soft_reset(void)
+{
+ focus_set_bits(CR, CR_SRESET);
+ focus_clear_bits(CR, CR_SRESET);
+}
+
+void focus_latch_nco_pll(void)
+{
+ focus_set_bits(CR, CR_NCO_EN);
+ focus_clear_bits(CR, CR_NCO_EN);
+ focus_set_bits(CR, CR_GCC_CK_LVL); //I don't think this applies to this operation
+}
+
+void focus_bridge_reset(void)
+{
+ focus_set_bits(MISC, MISC_BRDG_RST);
+ OS_mdelay(100);
+ focus_clear_bits(MISC, MISC_BRDG_RST);
+}
+
+void focus_set_qpr(FOCUS_VIDEO_OUTPUT_FORMAT format)
+{
+ uint32 qpr = QK_PROGRAM | QK_FF | QK_UIM_NATIONAL;
+
+ switch(format)
+ {
+ case FORMAT_HDTV: qpr |= QK_OS_480P | QK_YC_IN | QK_OM_COMPONENT | QK_GMODE_720X480;
+ break;
+ case FORMAT_COMPONENT: qpr |= QK_OS_SDTV | QK_OM_COMPONENT | QK_GMODE_640X480;
+ break;
+ case FORMAT_CVSV: qpr |= QK_OS_SDTV | QK_OM_CVSV | QK_GMODE_640X480;
+ break;
+ }
+
+ focus_write(QPR, qpr);
+}
+
+void focus_set_video_mode(FOCUS_VIDEO_OUTPUT_FORMAT format)
+{
+ focus_clear_bits(VID_CNTRL0, 0x3); //zero out current video mode
+
+ switch(format)
+ {
+ case FORMAT_HDTV: focus_set_bits(MISC_47, MISC_47_COMP_YUV);
+ focus_set_bits(VID_CNTRL0, VID_MODE_HDTV);
+ break;
+ case FORMAT_COMPONENT: focus_set_bits(MISC_47, MISC_47_COMP_YUV);
+ focus_set_bits(VID_CNTRL0, VID_MODE_SDTV);
+ break;
+ case FORMAT_CVSV: focus_set_bits(VID_CNTRL0, VID_MODE_CVSV);
+ break;
+ }
+}
+
+void focus_reg_dump(void)
+{
+ int i;
+ for(i = 0; focus_registers[i].id != UNDEFINED_REGISTER; ++i)
+ {
+ OS_printf("%12s (0x%02X) = 0x%X\n", focus_registers[i].description, focus_registers[i].address, focus_read(focus_registers[i].id));
+ }
+}
+
+int board_au1200fb_focus_shutdown(void)
+{
+ SIOLL_shutdown_focus();
+ return 1;
+}
+
+int focus_init(FOCUS_VIDEO_OUTPUT_FORMAT format, const FOCUS_REGISTER_VALUE* regs)
+{
+ int i;
+ if(regs == NULL)
+ return 0;
+
+ SIOLL_init_focus();
+ SIO_init();
+
+ focus_clear_bits(CR, CR_NCO_EN | CR_SRESET);
+
+ focus_set_qpr(format);
+
+ focus_soft_reset();
+
+ //Program configuration
+ for(i = 0; regs[i].id != UNDEFINED_REGISTER; ++i)
+ focus_write(regs[i].id, regs[i].value);
+
+ focus_latch_nco_pll();
+
+ focus_bridge_reset();
+
+ //Clear the CACQ and FIFO flags
+ focus_set_bits(CR, CR_FIFO_CLR | CR_CACQ_CLR);
+ OS_mdelay(100);
+ focus_clear_bits(CR, CR_FIFO_CLR | CR_CACQ_CLR);
+
+ focus_set_video_mode(format);
+
+// focus_reg_dump();
+ SIO_shutdown();
+
+ return 1;
+}
+
+int board_au1200fb_focus_init_component(void)
+{
+ return focus_init(FORMAT_COMPONENT, register_set_sdtv);
+}
+
+int board_au1200fb_focus_init_cvsv(void)
+{
+ return focus_init(FORMAT_CVSV, register_set_sdtv);
+}
+
+int board_au1200fb_focus_init_hdtv(void)
+{
+ return focus_init(FORMAT_HDTV, register_set_hdtv);
+}
+
diff -Naur linux26-cvs/drivers/video/focus/focus.h linux26-fs4553/drivers/video/focus/focus.h--- linux26-cvs/drivers/video/focus/focus.h 1969-12-31 18:00:00.000000000 -0600+++ linux26-fs4553/drivers/video/focus/focus.h 2005-08-12 10:18:29.000000000 -0500@@ -0,0 +1,315 @@+#ifndef FOCUS_H
+#define FOCUS_H
+
+typedef enum
+{
+ FORMAT_CVSV,
+ FORMAT_COMPONENT,
+ FORMAT_HDTV
+} FOCUS_VIDEO_OUTPUT_FORMAT;
+
+//FOCUS SMBus Device Address
+#define FS453_ADDRESS 0x6A
+
+//FOCUS Bit Definitions
+//CR Register
+#define CR_FIFO_CLR (1<<6)
+#define CR_CACQ_CLR (1<<5)
+#define CR_NCO_EN (1<<1)
+#define CR_SRESET (1<<0)
+#define CR_GCC_CK_LVL (1<<13)
+#define CR_CBAR_480P (1<<9)
+//MISC Register
+#define MISC_BRDG_RST (1<<10)
+#define MISC_47_COMP_YUV (1<<2)
+//VIDMODE0 Register
+#define VID_MODE_CVSV 0
+#define VID_MODE_SDTV 1
+#define VID_MODE_SCART 1
+#define VID_MODE_HDTV 2
+#define VID_MODE_VGA 2
+//QPR Register
+#define QK_PROGRAM (9<<12)
+#define QK_UIM_NATIONAL (3<<10)
+#define QK_OS_SDTV (0<<8)
+#define QK_OS_480P (1<<8)
+#define QK_YC_IN (1<<7)
+#define QK_FF (1<<6)
+#define QK_OM_CVSV (0<<4)
+#define QK_OM_COMPONENT (1<<4)
+#define QK_UO (1<<3)
+#define QK_GMODE_640X480 (0<<1)
+#define QK_GMODE_720X480 (1<<1)
+#define QK_PN (1<<0)
+
+typedef enum
+{
+ IHO,
+ IVO,
+ IHW,
+ VSC,
+ HSC,
+ BYPASS,
+ CR,
+ MISC,
+ NCON,
+ NCOD,
+ PLL_M,
+ PLL_N,
+ PLL_PD,
+ SHP,
+ FLK,
+ GPIO,
+ ID,
+ STATUS_PORT,
+ FIFO_SP,
+ FIFO_LAT,
+ VSOUT_TOTAL,
+ VSOUT_START,
+ VSOUT_END,
+ CHR_FREQ,
+ CHR_PHASE,
+ MISC_45,
+ MISC_46,
+ MISC_47,
+ HSYNC_WID,
+ BURST_WID,
+ BPORCH,
+ CB_BURST,
+ CR_BURST,
+ MISC_4D,
+ BLACK_LVL,
+ BLANK_LVL,
+ NUM_LINES,
+ WHITE_LVL,
+ CB_GAIN,
+ CR_GAIN,
+ TINT,
+ BR_WAY,
+ FR_PORCH,
+ NUM_PIXELS,
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