cymometer.vhd

vhdl 实现的频率计

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity cymometer is
    port(areset:in std_logic;
         aclk:in std_logic;
         testsignal:in std_logic;
         display1:out std_logic_vector(0 to 6);
         display2:out std_logic_vector(0 to 6);
         display3:out std_logic_vector(0 to 6);
         dot:out std_logic_vector(0 to 2));
end cymometer;

architecture cym of cymometer is
type state is(start,judge,count1,count2to89,count90,
              count91to98,count99,count100);

signal mycrm:state;
signal crmcou:integer range 0 to 99;
signal clk1k:std_logic;
signal cou1k:integer range 0 to 9999;
signal encrm:std_logic;
signal flag:std_logic_vector(2 downto 0);
signal keepcou1:std_logic_vector(3 downto 0);
signal keepcou2:std_logic_vector(3 downto 0);
signal keepcou3:std_logic_vector(3 downto 0);
signal ttclk:std_logic;
signal ttsig:std_logic;

component view is
    port(in_data:in std_logic_vector(3 downto 0);
         out_data:out std_logic_vector(0 to 6));
end component;

component counter is
    port(reset:in std_logic;
         clk:in std_logic;
         sig:in std_logic;
         keep1:out std_logic_vector(3 downto 0);
         keep2:out std_logic_vector(3 downto 0);
         keep3:out std_logic_vector(3 downto 0));
end component;

begin
crc1k:process(areset,aclk)
begin
   if areset='1' then
      cou1k<=0;
      clk1k<='0';
   else
      if aclk'event and aclk='1' then
         if cou1k= 9999 then
            cou1k<=0;
            clk1k<=not clk1k;
         else
            cou1k<=cou1k+1;
         end if;
      end if;
   end if;
end process crc1k;

crdot:process(flag)
begin
   case flag is
       when "000"=> dot <="000";
       when "001"=> dot <="100";
       when "010"=> dot <="010";
       when "011"=> dot <="001";
       when others=> dot <="111";
   end case;
end process crdot;

crfre:process(areset,clk1k)
begin
   if areset= '1' then
      crmcou<=0;
      encrm<='0';
      flag<="001";
      mycrm<=start;
   else
     if clk1k'event and clk1k='1' then
        case mycrm is
            when start=>
                        crmcou<=0;
                        encrm<='0';
                        flag<="111";
                        mycrm<=judge;
            when judge=>
            if flag ="000" then
               if keepcou1="0000" and keepcou2="0000" and
                  keepcou3="0000" then
                    flag<="001";
                    encrm<='1';
                else
                    flag<="000";
                end if;
            elsif flag ="100" then
               if keepcou3="1010" then
                    flag<="100";
               else
                    flag<="011";
               end if;
           elsif flag ="010" then
               if keepcou3="0001" then
                    flag<=flag-1;
                    encrm<= '1';
               elsif keepcou3="1010" then
                    flag<=flag+1;
               end if;
           elsif flag ="001" then
               if keepcou3="0001" then
                    flag<=flag-1;
                    encrm<='1';
               elsif keepcou3="1010" then
                    flag<=flag+1;
               else 
                    flag<=flag;
                    encrm<='1';
               end if;
           end if;
           mycrm<=count1;
         when count1=>
                  if flag="001" or flag="000" then
                         encrm<='1';
                  else 
                         encrm<=encrm;
                  end if;
                  crmcou<=1;
                  mycrm<=count2to89;
              when count2to89=>
                       if crmcou=88 then
                          crmcou<=89;
                          mycrm<=count90;
                       else
                          crmcou<=crmcou+1;
                          mycrm<=count2to89;
                       end if;
                    when count90=>
                         if flag="010" then
                            encrm<='1';
                         else
                            encrm<=encrm;
                          end if;
                      crmcou<=90;
                      mycrm<=count91to98;
                    when count91to98=>
                       if crmcou=97 then
                          crmcou<=98;
                          mycrm<=count99;
                       else
                          crmcou<=crmcou+1;
                          mycrm<=count91to98;
                       end if;
                   when count99=>
                  if flag="011" or flag="100" then
                         encrm<='1';
                  else 
                         encrm<=encrm;
                  end if;
                  crmcou<=99;
                  mycrm<=count100;
                 when count100=>
                    crmcou<=100;
                    encrm<='0';
                    mycrm<=judge;
                   when others =>null;
                end case;
              end if;
         end if;
  end process crfre;

crtt:process(areset,flag)
begin
  if areset='1' then
       ttclk<='0';
       ttsig<='0';
  else
       ttclk<=testsignal;
       ttsig<=encrm;
 end if;
end process;

couter_1:counter port map(areset,ttclk,ttsig,keepcou1,keepcou2,keepcou3); 
display_1:view port map(keepcou1,display1);
display_2:view port map(keepcou2,display2);
display_3:view port map(keepcou3,display3);
end cym;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity counter is
port(reset:in std_logic;
         clk:in std_logic;
         sig:in std_logic;
         keep1:out std_logic_vector(3 downto 0);
         keep2:out std_logic_vector(3 downto 0);
         keep3:out std_logic_vector(3 downto 0));
end counter;

architecture count of counter is
  signal cou1:std_logic_vector(3 downto 0);
  signal cou2:std_logic_vector(3 downto 0);
  signal cou3:std_logic_vector(3 downto 0);
begin
     ctrcou:process(reset,clk)
         begin
           if reset='1' then
              cou1<="0000";
              cou2<="0000";
              cou3<="0000";
           else
           if clk'event and clk ='1' then
           if sig='1' then
           if cou3="1010" then
              cou3<="1010";
           else
           if cou1="1001" and cou2="1001" and cou3="1001" then
              cou1<="0000";
              cou2<="0000";
              cou3<="1010";
           elsif cou1="1001" and cou2="1001" then
              cou1<="0000";
              cou2<="0000";
              cou3<=cou3+1;
          elsif cou1="1001" then
              cou1<="0000";
              cou2<=cou2+1;
          else 
              cou1<=cou1+1;
          end if;
          end if;
          else 
              cou1<="0000";
              cou2<="0000";
              cou3<="0000";
          end if;
          end if;
          end if; 
          end process ctrcou;


cpuctr:process(reset,sig)
 begin
       if reset='1' then
          keep1<="0000";
          keep2<="0000";
          keep3<="0000";
       else
          if sig'event and sig ='0' then
          keep1<=cou1;
          keep2<=cou2;
          keep3<=cou3;
       end if;
    end if;
end process cpuctr;
end count; 

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity view is
  port(in_data:in std_logic_vector(3 downto 0);
         out_data:out std_logic_vector(0 to 6));
end view;

architecture ouview of view is
   signal indata:std_logic_vector(3 downto 0);
begin
   process(in_data)
   begin
    indata<=in_data;
   case indata is
     when "0000"=>out_data<="1111110";
     when "0001"=>out_data<="0110000";
     when "0010"=>out_data<="1101101";
     when "0011"=>out_data<="1111001";
     when "0100"=>out_data<="0110011";
     when "0101"=>out_data<="1011011";
     when "0110"=>out_data<="1011111";
     when "0111"=>out_data<="1110000";
     when "1000"=>out_data<="1111111";
     when "1001"=>out_data<="1111011";
     when others=>out_data<="0110001";
   end case;
end process;
end ouview;