testman_fpga.vhd

FPGA分频 控制4个LED连续闪烁 形成累加的效果

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity testman_fpga is
	port
	(
	sys_clk		: in std_logic;
	--pgood		: in std_logic;
	Hdreset		: in std_logic;	  
	
	--TestPin		: out std_logic;
	lamp4		: out std_logic_vector(3 downto 0)
	);
end testman_fpga;

architecture rtl of testman_fpga is


signal sys_clk_cnt		: std_logic_vector(23 downto 0) := (others => '0');

signal clk				: std_logic := '0';	 
signal reset			: std_logic := '0';

begin
	
	reset <= not Hdreset;
	--reset <= not(pgood and Hdreset);
	clk	<= sys_clk;
	
	
	process(reset, clk)
	begin
		    if reset = '1' then                                --if (reset = '1') OR (PGOOD = '1') then
			sys_clk_cnt	 <= (others => '0');
		elsif rising_edge(clk) then
			sys_clk_cnt  <= sys_clk_cnt + 1;
		end if;	
	end process;
	
	lamp4(0) <= sys_clk_cnt(20);
	lamp4(1) <=	sys_clk_cnt(21);
	lamp4(2) <=	sys_clk_cnt(22);
	lamp4(3) <=	sys_clk_cnt(23);	  
	
	--TestPin <= '1';
	
end rtl;