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📄 wed.wsf

📁 This file is gotten from the web.
💻 WSF
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/

/*
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.
*/

VECTOR("D:/altera/61/quartus/zwork/cpld/icpld.vwf")
{
	ZOOM{
		ZBEGIN = 0;
		ZEND = 217200;
		NUMERATOR = 543;
		DENOMINATOR = 217200;
		TOP_INDEX = 0;
	}
	CLOCK{
		PERIOD = 10000;
		OFFSET = 0;
		DUTY_CYCLE = 50;
	}
	RANDOM_VALUE{
		INTERVAL_TYPE = HALF_GRID;
	}
	LINE{
		SIGNAL = "CPU_RST";
		INDEX = 0;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "MCU_RST_CTRL";
		INDEX = 1;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "FPGA_RESET";
		INDEX = 2;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "SWITCH_MODE";
		INDEX = 3;
		FORMAT = T;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "SWITCH_MODE[2]";
		INDEX = 4;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "SWITCH_MODE[1]";
		INDEX = 5;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "SWITCH_MODE[0]";
		INDEX = 6;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "SWCLK";
		INDEX = 7;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "EXT_CLK";
		INDEX = 8;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "MCU_CLK";
		INDEX = 9;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "FPGA_CLK";
		INDEX = 10;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "FPGA2RAM_DATA_EN";
		INDEX = 11;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "FPGA_RD";
		INDEX = 12;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "FPGA_WR";
		INDEX = 13;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "FPGA2RAM_DATA_DIR";
		INDEX = 14;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "RAM_OE";
		INDEX = 15;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "RAM_WR";
		INDEX = 16;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "RAM_EN";
		INDEX = 17;
		FORMAT = T;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "RAM_EN[3]";
		INDEX = 18;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "RAM_EN[2]";
		INDEX = 19;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "RAM_EN[1]";
		INDEX = 20;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "RAM_EN[0]";
		INDEX = 21;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "MCU_CODE";
		INDEX = 22;
		FORMAT = T;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "MCU_CODE[3]";
		INDEX = 23;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "MCU_CODE[2]";
		INDEX = 24;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "MCU_CODE[1]";
		INDEX = 25;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "MCU_CODE[0]";
		INDEX = 26;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "MCU_SEL";
		INDEX = 27;
		FORMAT = T;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "MCU_SEL[11]";
		INDEX = 28;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "MCU_SEL[10]";
		INDEX = 29;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "MCU_SEL[9]";
		INDEX = 30;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "MCU_SEL[8]";
		INDEX = 31;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "MCU_SEL[7]";
		INDEX = 32;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "MCU_SEL[6]";
		INDEX = 33;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "MCU_SEL[5]";
		INDEX = 34;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "MCU_SEL[4]";
		INDEX = 35;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "MCU_SEL[3]";
		INDEX = 36;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "MCU_SEL[2]";
		INDEX = 37;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "MCU_SEL[1]";
		INDEX = 38;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "MCU_SEL[0]";
		INDEX = 39;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
}

VECTOR("D:/altera/61/quartus/zwork/cpld/db/icpld.sim.cvwf")
{
	ZOOM{
		ZBEGIN = 301018;
		ZEND = 426177;
		NUMERATOR = 430;
		DENOMINATOR = 125159;
		TOP_INDEX = 3;
	}
	CLOCK{
		PERIOD = 10000;
		OFFSET = 0;
		DUTY_CYCLE = 50;
	}
	RANDOM_VALUE{
		INTERVAL_TYPE = HALF_GRID;
	}
	LINE{
		SIGNAL = "CPU_RST";
		INDEX = 0;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "MCU_RST_CTRL";
		INDEX = 1;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "FPGA_RESET";
		INDEX = 2;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "SWITCH_MODE";
		INDEX = 3;
		FORMAT = T;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "SWITCH_MODE[2]";
		INDEX = 4;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "SWITCH_MODE[1]";
		INDEX = 5;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "SWITCH_MODE[0]";
		INDEX = 6;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "SWCLK";
		INDEX = 7;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "EXT_CLK";
		INDEX = 8;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "MCU_CLK";
		INDEX = 9;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "FPGA_CLK";
		INDEX = 10;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "FPGA2RAM_DATA_EN";
		INDEX = 11;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "FPGA_RD";
		INDEX = 12;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "FPGA_WR";
		INDEX = 13;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "FPGA2RAM_DATA_DIR";
		INDEX = 14;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "RAM_OE";
		INDEX = 15;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "RAM_WR";
		INDEX = 16;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "RAM_EN";
		INDEX = 17;
		FORMAT = T;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "RAM_EN[3]";
		INDEX = 18;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "RAM_EN[2]";
		INDEX = 19;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "RAM_EN[1]";
		INDEX = 20;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "RAM_EN[0]";
		INDEX = 21;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "MCU_CODE";
		INDEX = 22;
		FORMAT = T;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "MCU_CODE[3]";
		INDEX = 23;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "MCU_CODE[2]";
		INDEX = 24;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "MCU_CODE[1]";
		INDEX = 25;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "MCU_CODE[0]";
		INDEX = 26;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "MCU_SEL";
		INDEX = 27;
		FORMAT = T;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "MCU_SEL[11]";
		INDEX = 28;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "MCU_SEL[10]";
		INDEX = 29;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "MCU_SEL[9]";
		INDEX = 30;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "MCU_SEL[8]";
		INDEX = 31;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "MCU_SEL[7]";
		INDEX = 32;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "MCU_SEL[6]";
		INDEX = 33;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "MCU_SEL[5]";
		INDEX = 34;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "MCU_SEL[4]";
		INDEX = 35;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "MCU_SEL[3]";
		INDEX = 36;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "MCU_SEL[2]";
		INDEX = 37;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "MCU_SEL[1]";
		INDEX = 38;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "MCU_SEL[0]";
		INDEX = 39;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "FREGSEL_LATCH_OE";
		INDEX = 40;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "DIPCTRL[0]";
		INDEX = 41;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "DIPCTRL[1]";
		INDEX = 42;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "TXD_CPLD";
		INDEX = 43;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "RAM_DATA_DIR";
		INDEX = 44;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "FPGA2RAM_ADDR_EN";
		INDEX = 45;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "RAM_ADDR_LATCH_OE";
		INDEX = 46;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
}

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