icpld.hier_info

This file is gotten from the web.

|icpld
SWITCH_MODE[0] => Mux0.IN2
SWITCH_MODE[0] => Mux1.IN10
SWITCH_MODE[0] => Mux2.IN10
SWITCH_MODE[0] => Mux3.IN9
SWITCH_MODE[0] => Mux4.IN9
SWITCH_MODE[0] => Mux5.IN9
SWITCH_MODE[0] => Mux6.IN9
SWITCH_MODE[0] => Decoder0.IN2
SWITCH_MODE[0] => Mux7.IN10
SWITCH_MODE[0] => Mux8.IN10
SWITCH_MODE[1] => Mux0.IN1
SWITCH_MODE[1] => Mux1.IN9
SWITCH_MODE[1] => Mux2.IN9
SWITCH_MODE[1] => Mux3.IN8
SWITCH_MODE[1] => Mux4.IN8
SWITCH_MODE[1] => Mux5.IN8
SWITCH_MODE[1] => Mux6.IN8
SWITCH_MODE[1] => Decoder0.IN1
SWITCH_MODE[1] => Mux7.IN9
SWITCH_MODE[1] => Mux8.IN9
SWITCH_MODE[2] => Mux0.IN0
SWITCH_MODE[2] => Mux1.IN8
SWITCH_MODE[2] => Mux2.IN8
SWITCH_MODE[2] => Mux3.IN7
SWITCH_MODE[2] => Mux4.IN7
SWITCH_MODE[2] => Mux5.IN7
SWITCH_MODE[2] => Mux6.IN7
SWITCH_MODE[2] => Decoder0.IN0
SWITCH_MODE[2] => Mux7.IN8
SWITCH_MODE[2] => Mux8.IN8
RAM_ADDR_LATCH[0] => ~NO_FANOUT~
RAM_ADDR_LATCH[1] => ~NO_FANOUT~
RAM_ADDR_LATCH[2] => ~NO_FANOUT~
RAM_DATA_SEL[0] => Mux6.IN10
RAM_DATA_SEL[1] => Mux5.IN10
RAM_DATA_SEL[2] => Mux4.IN10
RAM_DATA_SEL[3] => Mux3.IN10
MCU_CODE[0] => MCU_SEL~12.DATAB
MCU_CODE[1] => MCU_SEL~11.DATAB
MCU_CODE[2] => MCU_SEL~10.DATAB
MCU_CODE[3] => MCU_SEL~9.DATAB
FREGSEL_LATCH_EN => ~NO_FANOUT~
RAM_EN[0] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
RAM_EN[1] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
RAM_EN[2] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
RAM_EN[3] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
RAM_OE <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
RAM_WR <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
RAM_DATA_DIR <= RAM_DATA_DIR~0.DB_MAX_OUTPUT_PORT_TYPE
RAM_ADDR_LATCH_OE <= RAM_ADDR_LATCH_OE$latch.DB_MAX_OUTPUT_PORT_TYPE
FREGSEL_LATCH_OE <= FREGSEL_LATCH_OE~1.DB_MAX_OUTPUT_PORT_TYPE
FPGA2RAM_DATA_EN <= FPGA2RAM_DATA_EN~1.DB_MAX_OUTPUT_PORT_TYPE
FPGA2RAM_DATA_DIR <= FPGA2RAM_DATA_DIR~0.DB_MAX_OUTPUT_PORT_TYPE
FPGA2RAM_ADDR_EN <= FPGA2RAM_ADDR_EN~0.DB_MAX_OUTPUT_PORT_TYPE
FPGA_CLK <= Mux0.DB_MAX_OUTPUT_PORT_TYPE
FPGA_RESET <= FPGA_RESET~0.DB_MAX_OUTPUT_PORT_TYPE
DIPCTRL[0] <= DIPCTRL~1.DB_MAX_OUTPUT_PORT_TYPE
DIPCTRL[1] <= DIPCTRL~0.DB_MAX_OUTPUT_PORT_TYPE
MCU_SEL[0] <= MCU_SEL~12.DB_MAX_OUTPUT_PORT_TYPE
MCU_SEL[1] <= MCU_SEL~11.DB_MAX_OUTPUT_PORT_TYPE
MCU_SEL[2] <= MCU_SEL~10.DB_MAX_OUTPUT_PORT_TYPE
MCU_SEL[3] <= MCU_SEL~9.DB_MAX_OUTPUT_PORT_TYPE
MCU_SEL[4] <= MCU_SEL~8.DB_MAX_OUTPUT_PORT_TYPE
MCU_SEL[5] <= MCU_SEL~7.DB_MAX_OUTPUT_PORT_TYPE
MCU_SEL[6] <= MCU_SEL~6.DB_MAX_OUTPUT_PORT_TYPE
MCU_SEL[7] <= MCU_SEL~5.DB_MAX_OUTPUT_PORT_TYPE
MCU_SEL[8] <= MCU_SEL~4.DB_MAX_OUTPUT_PORT_TYPE
MCU_SEL[9] <= MCU_SEL~3.DB_MAX_OUTPUT_PORT_TYPE
MCU_SEL[10] <= MCU_SEL~2.DB_MAX_OUTPUT_PORT_TYPE
MCU_SEL[11] <= MCU_SEL~1.DB_MAX_OUTPUT_PORT_TYPE
FPGA_RD => always0~0.IN0
FPGA_RD => always0~3.IN1
FPGA_RD => always0~4.IN0
FPGA_WR => always0~1.IN1
FPGA_WR => always0~2.IN0
FPGA_WR => always0~4.IN1
CPU_RST => FPGA_RESET~0.DATAB
EXT_CLK => Mux0.IN3
MCU_RST_CTRL => FPGA_RESET~0.DATAA
MCU_CLK => Mux0.IN4
MCU_CLK => Mux0.IN5
MCU_CLK => Mux0.IN6
MCU_CLK => Mux0.IN7
MCU_CLK => Mux0.IN8
MCU_RD => always0~5.IN0
MCU_RD => always0~8.IN1
MCU_WR => always0~6.IN1
MCU_WR => always0~7.IN0
SWCLK => Mux0.IN9
SWCLK => Mux0.IN10
RXD_CPLD => ~NO_FANOUT~
RS_CLK => ~NO_FANOUT~
PS2KB_DATA => ~NO_FANOUT~
PS2MOUSE_DATA => ~NO_FANOUT~
TXD_CPLD <= <GND>
PS2KB_CLOCK <= <UNC>
PS2MOUSE_CLOCK <= <UNC>
LCD_CTRL[0] <= <GND>
LCD_CTRL[1] <= <GND>
LCD_CTRL[2] <= <GND>
LCD_DATA[0] <= <GND>
LCD_DATA[1] <= <GND>
LCD_DATA[2] <= <GND>
LCD_DATA[3] <= <GND>
LCD_DATA[4] <= <GND>
LCD_DATA[5] <= <GND>
LCD_DATA[6] <= <GND>
LCD_DATA[7] <= <GND>
FPGA_ADDR[0] => ~NO_FANOUT~
FPGA_ADDR[1] => ~NO_FANOUT~
FPGA_ADDR[2] => ~NO_FANOUT~
FPGA_ADDR[3] => ~NO_FANOUT~
FPGA_ADDR[4] => ~NO_FANOUT~
FPGA_ADDR[5] => ~NO_FANOUT~
FPGA_ADDR[6] => ~NO_FANOUT~
FPGA_ADDR[7] => ~NO_FANOUT~
FPGA_DATA[0] <= <UNC>
FPGA_DATA[1] <= <UNC>
FPGA_DATA[2] <= <UNC>
FPGA_DATA[3] <= <UNC>
FPGA_DATA[4] <= <UNC>
FPGA_DATA[5] <= <UNC>
FPGA_DATA[6] <= <UNC>
FPGA_DATA[7] <= <UNC>
INTr[0] <= <GND>
INTr[1] <= <GND>
INTr[2] <= <GND>
INTr[3] <= <GND>