icpld.fit.rpt

This file is gotten from the web.

Fitter report for icpld
Tue Mar 04 16:28:55 2008
Quartus II Version 6.1 Build 201 11/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Pin-Out File
  5. Fitter Resource Usage Summary
  6. Input Pins
  7. Output Pins
  8. Bidir Pins
  9. All Package Pins
 10. Output Pin Default Load For Reported TCO
 11. Fitter Resource Utilization by Entity
 12. Non-Global High Fan-Out Signals
 13. Interconnect Usage Summary
 14. LAB External Interconnect
 15. LAB Macrocells
 16. Parallel Expander
 17. Logic Cell Interconnection
 18. Fitter Device Options
 19. Fitter Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------+
; Fitter Summary                                                   ;
+-----------------------+------------------------------------------+
; Fitter Status         ; Successful - Tue Mar 04 16:28:55 2008    ;
; Quartus II Version    ; 6.1 Build 201 11/27/2006 SJ Full Version ;
; Revision Name         ; icpld                                    ;
; Top-level Entity Name ; icpld                                    ;
; Family                ; MAX3000A                                 ;
; Device                ; EPM3256AQC208-10                         ;
; Timing Models         ; Final                                    ;
; Total macrocells      ; 73 / 256 ( 29 % )                        ;
; Total pins            ; 94 / 158 ( 59 % )                        ;
+-----------------------+------------------------------------------+


+-------------------------------------------------------------------------------+
; Fitter Settings                                                               ;
+--------------------------------------------+------------------+---------------+
; Option                                     ; Setting          ; Default Value ;
+--------------------------------------------+------------------+---------------+
; Device                                     ; EPM3256AQC208-10 ;               ;
; Optimize IOC Register Placement for Timing ; On               ; On            ;
; Limit to One Fitting Attempt               ; Off              ; Off           ;
; Fitter Initial Placement Seed              ; 1                ; 1             ;
; Slow Slew Rate                             ; Off              ; Off           ;
; Fitter Effort                              ; Auto Fit         ; Auto Fit      ;
; Use smart compilation                      ; Off              ; Off           ;
+--------------------------------------------+------------------+---------------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in D:/altera/61/quartus/zwork/cpld/icpld.pin.


+-------------------------------------------------------+
; Fitter Resource Usage Summary                         ;
+-----------------------------------+-------------------+
; Resource                          ; Usage             ;
+-----------------------------------+-------------------+
; Logic cells                       ; 73 / 256 ( 29 % ) ;
; Registers                         ; 0 / 256 ( 0 % )   ;
; Number of pterms used             ; 139               ;
; User inserted logic elements      ; 0                 ;
; I/O pins                          ; 94 / 158 ( 59 % ) ;
;     -- Clock pins                 ; 0 / 2 ( 0 % )     ;
;     -- Dedicated input pins       ; 0 / 2 ( 0 % )     ;
; Global signals                    ; 0                 ;
; Shareable expanders               ; 0 / 256 ( 0 % )   ;
; Parallel expanders                ; 15 / 240 ( 6 % )  ;
; Cells using turbo bit             ; 73 / 256 ( 29 % ) ;
; Maximum fan-out node              ; SWITCH_MODE[0]    ;
; Maximum fan-out                   ; 41                ;
; Highest non-global fan-out signal ; SWITCH_MODE[0]    ;
; Highest non-global fan-out        ; 41                ;
; Total fan-out                     ; 220               ;
; Average fan-out                   ; 1.32              ;
+-----------------------------------+-------------------+


+----------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                             ;
+-------------------+-------+----------+-----+-----------------------+--------------------+--------+--------------+----------------------+
; Name              ; Pin # ; I/O Bank ; LAB ; Combinational Fan-Out ; Registered Fan-Out ; Global ; I/O Standard ; Location assigned by ;
+-------------------+-------+----------+-----+-----------------------+--------------------+--------+--------------+----------------------+
; CPU_RST           ; 7     ; --       ; 14  ; 1                     ; 0                  ; no     ; 3.3-V LVTTL  ; User                 ;
; EXT_CLK           ; 13    ; --       ; 14  ; 1                     ; 0                  ; no     ; 3.3-V LVTTL  ; User                 ;
; FPGA_ADDR[0]      ; 55    ; --       ; 16  ; 0                     ; 0                  ; no     ; 3.3-V LVTTL  ; User                 ;
; FPGA_ADDR[1]      ; 56    ; --       ; 16  ; 0                     ; 0                  ; no     ; 3.3-V LVTTL  ; User                 ;
; FPGA_ADDR[2]      ; 57    ; --       ; 16  ; 0                     ; 0                  ; no     ; 3.3-V LVTTL  ; User                 ;
; FPGA_ADDR[3]      ; 58    ; --       ; 16  ; 0                     ; 0                  ; no     ; 3.3-V LVTTL  ; User                 ;
; FPGA_ADDR[4]      ; 59    ; --       ; 16  ; 0                     ; 0                  ; no     ; 3.3-V LVTTL  ; User                 ;
; FPGA_ADDR[5]      ; 60    ; --       ; 16  ; 0                     ; 0                  ; no     ; 3.3-V LVTTL  ; User                 ;
; FPGA_ADDR[6]      ; 61    ; --       ; 16  ; 0                     ; 0                  ; no     ; 3.3-V LVTTL  ; User                 ;
; FPGA_ADDR[7]      ; 62    ; --       ; 16  ; 0                     ; 0                  ; no     ; 3.3-V LVTTL  ; User                 ;
; FPGA_RD           ; 3     ; --       ; 13  ; 7                     ; 0                  ; no     ; 3.3-V LVTTL  ; User                 ;
; FPGA_WR           ; 4     ; --       ; 13  ; 7                     ; 0                  ; no     ; 3.3-V LVTTL  ; User                 ;
; FREGSEL_LATCH_EN  ; 121   ; --       ; 7   ; 0                     ; 0                  ; no     ; 3.3-V LVTTL  ; User                 ;
; MCU_CLK           ; 12    ; --       ; 14  ; 1                     ; 0                  ; no     ; 3.3-V LVTTL  ; User                 ;
; MCU_CODE[0]       ; 73    ; --       ; 12  ; 1                     ; 0                  ; no     ; 3.3-V LVTTL  ; User                 ;
; MCU_CODE[1]       ; 76    ; --       ; 12  ; 1                     ; 0                  ; no     ; 3.3-V LVTTL  ; User                 ;
; MCU_CODE[2]       ; 77    ; --       ; 12  ; 1                     ; 0                  ; no     ; 3.3-V LVTTL  ; User                 ;