📄 icpld.map.rpt
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Analysis & Synthesis report for icpld
Tue Mar 04 16:28:51 2008
Quartus II Version 6.1 Build 201 11/27/2006 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Resource Usage Summary
6. Analysis & Synthesis Resource Utilization by Entity
7. User-Specified and Inferred Latches
8. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Tue Mar 04 16:28:51 2008 ;
; Quartus II Version ; 6.1 Build 201 11/27/2006 SJ Full Version ;
; Revision Name ; icpld ;
; Top-level Entity Name ; icpld ;
; Family ; MAX3000A ;
; Total macrocells ; 69 ;
; Total pins ; 90 ;
+-----------------------------+------------------------------------------+
+---------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+----------------------------------------------------------------------+------------------+---------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------------+------------------+---------------+
; Device ; EPM3256AQC208-10 ; ;
; Top-level entity name ; icpld ; icpld ;
; Family name ; MAX3000A ; Stratix ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A ; Auto ; Auto ;
; Ignore SOFT Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A ; Off ; Off ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique -- MAX 7000B/7000AE/3000A/7000S/7000A ; Speed ; Speed ;
; Allow XOR Gate Usage ; On ; On ;
; Auto Logic Cell Insertion ; On ; On ;
; Parallel Expander Chain Length -- MAX 7000B/7000AE/3000A/7000S/7000A ; 4 ; 4 ;
; Auto Parallel Expanders ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Auto Resource Sharing ; Off ; Off ;
; Maximum Fan-in Per Macrocell -- MAX 7000B/7000AE/3000A/7000S/7000A ; 100 ; 100 ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
; Use smart compilation ; Off ; Off ;
+----------------------------------------------------------------------+------------------+---------------+
+-----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------+-----------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------+-----------------------------------------+
; icpld.v ; yes ; User Verilog HDL File ; D:/altera/61/quartus/zwork/cpld/icpld.v ;
+----------------------------------+-----------------+------------------------+-----------------------------------------+
+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------+----------------------+
; Resource ; Usage ;
+----------------------+----------------------+
; Logic cells ; 69 ;
; Total registers ; 0 ;
; I/O pins ; 90 ;
; Parallel expanders ; 15 ;
; Maximum fan-out node ; SWITCH_MODE[0] ;
; Maximum fan-out ; 41 ;
; Total fan-out ; 216 ;
; Average fan-out ; 1.36 ;
+----------------------+----------------------+
+----------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+------------+------+---------------------+
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ;
+----------------------------+------------+------+---------------------+
; |icpld ; 69 ; 90 ; |icpld ;
+----------------------------+------------+------+---------------------+
+---------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches ;
+----------------------------------------------------+---------------------+------------------------+
; Latch Name ; Latch Enable Signal ; Free of Timing Hazards ;
+----------------------------------------------------+---------------------+------------------------+
; RAM_ADDR_LATCH_OE$latch ; Mux8 ; yes ;
; Number of user-specified and inferred latches = 1 ; ; ;
+----------------------------------------------------+---------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
Info: Processing started: Tue Mar 04 16:28:50 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off icpld -c icpld
Info: Found 1 design units, including 1 entities, in source file icpld.v
Info: Found entity 1: icpld
Info: Elaborating entity "icpld" for the top level hierarchy
Warning (10240): Verilog HDL Always Construct warning at icpld.v(167): inferring latch(es) for variable "RAM_ADDR_LATCH_OE", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at icpld.v(27): inferred latch for "RAM_ADDR_LATCH_OE"
Warning (10034): Output port "TXD_CPLD" at icpld.v(16) has no driver
Warning (10034): Output port "LCD_CTRL[2]" at icpld.v(18) has no driver
Warning (10034): Output port "LCD_CTRL[1]" at icpld.v(18) has no driver
Warning (10034): Output port "LCD_CTRL[0]" at icpld.v(18) has no driver
Warning (10034): Output port "LCD_DATA[7]" at icpld.v(19) has no driver
Warning (10034): Output port "LCD_DATA[6]" at icpld.v(19) has no driver
Warning (10034): Output port "LCD_DATA[5]" at icpld.v(19) has no driver
Warning (10034): Output port "LCD_DATA[4]" at icpld.v(19) has no driver
Warning (10034): Output port "LCD_DATA[3]" at icpld.v(19) has no driver
Warning (10034): Output port "LCD_DATA[2]" at icpld.v(19) has no driver
Warning (10034): Output port "LCD_DATA[1]" at icpld.v(19) has no driver
Warning (10034): Output port "LCD_DATA[0]" at icpld.v(19) has no driver
Warning (10034): Output port "INTr[3]" at icpld.v(23) has no driver
Warning (10034): Output port "INTr[2]" at icpld.v(23) has no driver
Warning (10034): Output port "INTr[1]" at icpld.v(23) has no driver
Warning (10034): Output port "INTr[0]" at icpld.v(23) has no driver
Warning: The bidir "PS2KB_CLOCK" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "PS2MOUSE_CLOCK" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "FPGA_DATA[0]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "FPGA_DATA[1]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "FPGA_DATA[2]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "FPGA_DATA[3]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "FPGA_DATA[4]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "FPGA_DATA[5]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "FPGA_DATA[6]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "FPGA_DATA[7]" has no source; inserted an always disabled tri-state buffer.
Warning: Output pins are stuck at VCC or GND
Warning: Pin "TXD_CPLD" stuck at GND
Warning: Pin "LCD_CTRL[0]" stuck at GND
Warning: Pin "LCD_CTRL[1]" stuck at GND
Warning: Pin "LCD_CTRL[2]" stuck at GND
Warning: Pin "LCD_DATA[0]" stuck at GND
Warning: Pin "LCD_DATA[1]" stuck at GND
Warning: Pin "LCD_DATA[2]" stuck at GND
Warning: Pin "LCD_DATA[3]" stuck at GND
Warning: Pin "LCD_DATA[4]" stuck at GND
Warning: Pin "LCD_DATA[5]" stuck at GND
Warning: Pin "LCD_DATA[6]" stuck at GND
Warning: Pin "LCD_DATA[7]" stuck at GND
Warning: Pin "INTr[0]" stuck at GND
Warning: Pin "INTr[1]" stuck at GND
Warning: Pin "INTr[2]" stuck at GND
Warning: Pin "INTr[3]" stuck at GND
Warning: Design contains 16 input pin(s) that do not drive logic
Warning: No output dependent on input pin "RAM_ADDR_LATCH[0]"
Warning: No output dependent on input pin "RAM_ADDR_LATCH[1]"
Warning: No output dependent on input pin "RAM_ADDR_LATCH[2]"
Warning: No output dependent on input pin "FREGSEL_LATCH_EN"
Warning: No output dependent on input pin "RXD_CPLD"
Warning: No output dependent on input pin "RS_CLK"
Warning: No output dependent on input pin "PS2KB_DATA"
Warning: No output dependent on input pin "PS2MOUSE_DATA"
Warning: No output dependent on input pin "FPGA_ADDR[0]"
Warning: No output dependent on input pin "FPGA_ADDR[1]"
Warning: No output dependent on input pin "FPGA_ADDR[2]"
Warning: No output dependent on input pin "FPGA_ADDR[3]"
Warning: No output dependent on input pin "FPGA_ADDR[4]"
Warning: No output dependent on input pin "FPGA_ADDR[5]"
Warning: No output dependent on input pin "FPGA_ADDR[6]"
Warning: No output dependent on input pin "FPGA_ADDR[7]"
Info: Implemented 159 device resources after synthesis - the final resource count might be different
Info: Implemented 36 input pins
Info: Implemented 44 output pins
Info: Implemented 10 bidirectional pins
Info: Implemented 69 macrocells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 61 warnings
Info: Allocated 117 megabytes of memory during processing
Info: Processing ended: Tue Mar 04 16:28:51 2008
Info: Elapsed time: 00:00:01
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