📄 main.c

📁 it is drive code for testing all function about ad5498
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	TW2[1]=0x66;
	TW2[0]=0x26;
	

	//sysclk=200MHz,△freq=100kHz
	DFW[5]=0xe3;
	DFW[4]=0xa5;
	DFW[3]=0x9b;
	DFW[2]=0xc4;
	DFW[1]=0x20;
	DFW[0]=0x00;

//sysclk=200MHz,△freq=10kHz
	DFW[5]=0x63;
	DFW[4]=0x5d;
	DFW[3]=0xdc;
	DFW[2]=0x46;
	DFW[1]=0x03;
	DFW[0]=0x00;

	//sysclk=200MHz,ramp is 5.2ms
//	RampRC[2]=0xff;
	RampRC[2]=0x00;
	RampRC[1]=0xff;
//	RampRC[0]=0x0f;
	RampRC[0]=0x07;
	//sysclk=200MHz,upclk time is 43s
	UpdateClk[3]=0xff;
	UpdateClk[2]=0xff;
	UpdateClk[1]=0xff;
	UpdateClk[0]=0xff;


	//sysclk=200MHz,upclk time is 1s
	UpdateClk[3]=0xff;
	UpdateClk[2]=0xff;
	UpdateClk[1]=0xc0;
	UpdateClk[0]=0xfa;

	//sysclk=200MHz,upclk time is 0.1s
	UpdateClk[3]=0x80;
	UpdateClk[2]=0x96;
	UpdateClk[1]=0x98;
	UpdateClk[0]=0x00;

	//sysclk=200MHz,upclk time is 1s
	UpdateClk[3]=0x00;
	UpdateClk[2]=0xe1;
	UpdateClk[1]=0xf5;
	UpdateClk[0]=0x05;

	ShapeKI[1]=0xff;
	ShapeKI[0]=0xff;

	ShapeKQ[1]=0xff;
	ShapeKQ[0]=0xff;

	PhaseAd1[1]=0;
	PhaseAd1[0]=0;

	PhaseAd2[1]=0xff;
	PhaseAd2[0]=0xff;

	ShapeKR=0xff;*/

	WriteRegByte(0x86,0x1f);//select ext clk,mode=011,CLRACC1=1
//	WriteRegByte(0x87,0x1f);//select int clk,mode=011,CLRACC1=1
	WriteReg(UpdateClk,0x16,4);
	WriteReg(ShapeKI,0x21,2);
	WriteReg(ShapeKQ,0x23,2);
	WriteRegByte(ShapeKR,0x25);
//	WriteRegByte(0x60,0x20);//to full-scale amplitude.
	WriteRegByte(0x40,0x20);//to full-scale amplitude.
//	WriteRegByte(0x0,0x20);//to full-scale amplitude.

	WriteReg(TW1,0x04,6);
	WriteReg(TW2,0x0a,6);
	WriteReg(DFW,0x10,6);
	WriteReg(RampRC,0x1a,3);
	//Note:when fbh=0,select mark2
	//the fequency start at 0Hz,stop till it reach tw1;
	//when fbh=0,and select mark1,fequency start at 0Hz , increase till
	//it reach 10*MHz,then decrease to 0Hz,and disappear,then recurrence
	fbh=0;
	shk=1;
	UpdatePin=1;
	UpdatePin=0;
	while(1)
	{
		if(UpdateFlag)
		{
			break;
		}
		UpdatePin=1;
		UpdatePin=0;
		for(i=0;i<20;i++);
		for(j=0;j<65535;j++);
		for(j=0;j<65535;j++);
		for(j=0;j<65535;j++);
		for(j=0;j<65535;j++);
		for(j=0;j<65535;j++);
		for(j=0;j<65535;j++);
	}

}

void Clracc2Chip(void)
{
	unsigned char i;
	unsigned int j;


/*	TW1[5]=0x99;//sysclk=200MHz,freq=20M
	TW1[4]=0x99;
	TW1[3]=0x99;
	TW1[2]=0x99;
	TW1[1]=0x99;
	TW1[0]=0x19;

	//sysclk=200MHz,△freq=100kHz
	DFW[5]=0xe3;
	DFW[4]=0xa5;
	DFW[3]=0x9b;
	DFW[2]=0xc4;
	DFW[1]=0x20;
	DFW[0]=0x00;

//sysclk=200MHz,△freq=10kHz
	DFW[5]=0x63;
	DFW[4]=0x5d;
	DFW[3]=0xdc;
	DFW[2]=0x46;
	DFW[1]=0x03;
	DFW[0]=0x00;


	//sysclk=200MHz,ramp is 5.2ms
//	RampRC[2]=0xff;
	RampRC[2]=0x00;
	RampRC[1]=0xff;
//	RampRC[0]=0x0f;
	RampRC[0]=0x07;

	RampRC[2]=0xff;
//	RampRC[2]=0x00;
	RampRC[1]=0xff;
	RampRC[0]=0x0f;
//	RampRC[0]=0x07;

	//sysclk=200MHz,upclk time is 43s
	UpdateClk[3]=0xff;
	UpdateClk[2]=0xff;
	UpdateClk[1]=0xff;
	UpdateClk[0]=0xff;


	//sysclk=200MHz,upclk time is 1s
	UpdateClk[3]=0xff;
	UpdateClk[2]=0xff;
	UpdateClk[1]=0xc0;
	UpdateClk[0]=0xfa;

	ShapeKI[1]=0xff;
	ShapeKI[0]=0xff;

	ShapeKQ[1]=0xff;
	ShapeKQ[0]=0xff;

	PhaseAd1[1]=0;
	PhaseAd1[0]=0;

	PhaseAd2[1]=0xff;
	PhaseAd2[0]=0xff;

	ShapeKR=0x00;*/

	WriteRegByte(0x46,0x1f);//select ext clk,mode=011,CLRACC2=1

	WriteReg(ShapeKI,0x21,2);
	WriteReg(ShapeKQ,0x23,2);
	WriteRegByte(ShapeKR,0x25);
	WriteRegByte(0x60,0x20);//to full-scale amplitude.


	WriteReg(TW1,0x04,6);
	WriteReg(DFW,0x10,6);
	WriteReg(RampRC,0x1a,3);

	fbh=0;
	UpdatePin=1;
	UpdatePin=0;
	while(1)
	{
		if(UpdateFlag)
		{
			break;
		}
		WriteRegByte(0x46,0x1f);//select ext clk,mode=011,CLRACC1=1
		UpdatePin=1;
	//	for(i=0;i<255;i++);
		UpdatePin=0;
		for(j=0;j<65535;j++);

		WriteRegByte(0x06,0x1f);//select ext clk,mode=011,CLRACC1=0
		UpdatePin=1;
	//	for(i=0;i<255;i++);
		UpdatePin=0;

		for(i=0;i<255;i++);
		for(i=0;i<255;i++);
		for(i=0;i<255;i++);
		for(i=0;i<255;i++);
		for(j=0;j<65535;j++);
	}
}

void RampFsk(void)
{
	unsigned char i;
	unsigned int j;


/*	TW2[5]=0x66;//freq=30M
	TW2[4]=0x66;
	TW2[3]=0x66;
	TW2[2]=0x66;
	TW2[1]=0x66;
	TW2[0]=0x26;
				
	TW1[5]=0x99;//freq=20M
	TW1[4]=0x99;
	TW1[3]=0x99;
	TW1[2]=0x99;
	TW1[1]=0x99;
	TW1[0]=0x19;
	
	//sysclk=200MHz,100kHz
	DFW[5]=0xe3;
	DFW[4]=0xa5;
	DFW[3]=0x9b;
	DFW[2]=0xc4;
	DFW[1]=0x20;
	DFW[0]=0x00;


	DFW[5]=0x63;
	DFW[4]=0x5d;
	DFW[3]=0xdc;
	DFW[2]=0x46;
	DFW[1]=0x03;
	DFW[0]=0x00;

//sysclk=200MHz,△freq=1MHz
	DFW[5]=0xe1;
	DFW[4]=0x7a;
	DFW[3]=0x14;
	DFW[2]=0xae;
	DFW[1]=0x47;
	DFW[0]=0x01;

//sysclk=200MHz,△freq=10kHz
	DFW[5]=0x63;
	DFW[4]=0x5d;
	DFW[3]=0xdc;
	DFW[2]=0x46;
	DFW[1]=0x03;
	DFW[0]=0x00;

	//sysclk=200MHz,△freq=5kHz
	DFW[5]=0xb1;
	DFW[4]=0x2e;
	DFW[3]=0x6e;
	DFW[2]=0xa3;
	DFW[1]=0x01;
	DFW[0]=0x00;

	//sysclk=200MHz,△freq=2kHz
	DFW[5]=0x47;
	DFW[4]=0xac;
	DFW[3]=0xc5;
	DFW[2]=0xa7;
	DFW[1]=0x00;
	DFW[0]=0x00;

//sysclk=200MHz,△freq=1kHz
	DFW[5]=0x23;
	DFW[4]=0xd6;
	DFW[3]=0xe2;
	DFW[2]=0x53;
	DFW[1]=0x00;
	DFW[0]=0x00;


	//step ramp is 5.2ms,sysclk=200MHz
//	RampRC[2]=0xff;
	RampRC[2]=0x0a;
	RampRC[1]=0xff;
	RampRC[0]=0x0f;


	//step ramp is 0.52ms,sysclk=200MHz
	RampRC[2]=0x99;
	RampRC[1]=0x99;
	RampRC[0]=0x01;

	//step ramp is 0.52ms,sysclk=200MHz
	RampRC[2]=0xfb;
	RampRC[1]=0x28;
	RampRC[0]=0x00;

	ShapeKI[1]=0xff;
	ShapeKI[0]=0xff;

	ShapeKQ[1]=0xff;
	ShapeKQ[0]=0xff;

	ShapeKR=0x00;*/

	fbh=1;
	WriteRegByte(0x04,0x1f);//select ext clk,mode=010
//	WriteRegByte(0x60,0x20);//to full-scale amplitude.
	WriteRegByte(0x0,0x20);//to full-scale amplitude.
	WriteReg(TW1,0x04,6);
	WriteReg(TW2,0x0a,6);
	WriteReg(DFW,0x10,6);
	WriteReg(RampRC,0x1a,3);

	WriteReg(ShapeKI,0x21,2);
	WriteReg(ShapeKQ,0x23,2);
	WriteRegByte(ShapeKR,0x25);

	UpdatePin=1;
	UpdatePin=0;
	while(1)
	{
		if(UpdateFlag)
		{
			break;
		}
		fbh=1;
		for(i=0;i<255;i++);
		for(i=0;i<255;i++);
		for(i=0;i<255;i++);
		for(i=0;i<255;i++);
		for(j=0;j<65535;j++);
		for(j=0;j<65535;j++);
		for(j=0;j<65535;j++);
		for(j=0;j<65535;j++);
		for(j=0;j<65535;j++);
		for(j=0;j<65535;j++);
		for(j=0;j<65535;j++);
		for(j=0;j<65535;j++);
		for(j=0;j<65535;j++);
		for(j=0;j<65535;j++);
		for(j=0;j<65535;j++);
		for(j=0;j<65535;j++);
		fbh=0;
		for(i=0;i<255;i++);
		for(i=0;i<255;i++);
		for(i=0;i<255;i++);
		for(i=0;i<255;i++);
		for(j=0;j<65535;j++);
		for(j=0;j<65535;j++);
		for(j=0;j<65535;j++);
		for(j=0;j<65535;j++);
		for(j=0;j<65535;j++);
		for(j=0;j<65535;j++);
		for(j=0;j<65535;j++);
		for(j=0;j<65535;j++);
		for(j=0;j<65535;j++);
		for(j=0;j<65535;j++);
		for(j=0;j<65535;j++);
	}
}

void TriFsk(void)
{
	unsigned int j;
/*	TW1[5]=0x99;//sysclk=200MHz,freq=20M
	TW1[4]=0x99;
	TW1[3]=0x99;
	TW1[2]=0x99;
	TW1[1]=0x99;
	TW1[0]=0x19;

	TW2[5]=0x66;//freq=30M
	TW2[4]=0x66;
	TW2[3]=0x66;
	TW2[2]=0x66;
	TW2[1]=0x66;
	TW2[0]=0x26;

	TW2[5]=0x00;//freq=50M
	TW2[4]=0x00;
	TW2[3]=0x00;
	TW2[2]=0x00;
	TW2[1]=0x00;
	TW2[0]=0x40;

	TW2[5]=0x00;//freq=25M
	TW2[4]=0x00;
	TW2[3]=0x00;
	TW2[2]=0x00;
	TW2[1]=0x00;
	TW2[0]=0x20;

	//sysclk=200MHz,△freq=1MHz
	DFW[5]=0xe1;
	DFW[4]=0x7a;
	DFW[3]=0x14;
	DFW[2]=0xae;
	DFW[1]=0x47;
	DFW[0]=0x01;

	//sysclk=200MHz,△freq=10kHz
	DFW[5]=0x63;
	DFW[4]=0x5d;
	DFW[3]=0xdc;
	DFW[2]=0x46;
	DFW[1]=0x03;
	DFW[0]=0x00;

	//sysclk=200MHz,ramp is 5.2ms
	RampRC[2]=0xff;
	RampRC[1]=0xff;
	RampRC[0]=0x0f;

		//sysclk=200MHz,ramp is 5.2ms
//	RampRC[2]=0xff;
	RampRC[2]=0xff;
	RampRC[1]=0xff;
//	RampRC[0]=0x0f;
	RampRC[0]=0x07;
	
	ShapeKI[1]=0xff;
	ShapeKI[0]=0xff;

	//half of full scall of amt
	ShapeKQ[1]=0x99;
	ShapeKQ[0]=0x01;
	ShapeKR=0x04;*/

	WriteReg(ShapeKI,0x21,2);
	WriteReg(ShapeKQ,0x23,2);
	WriteReg(RampRC,0x1a,3);

	WriteRegByte(ShapeKR,0x25);
	WriteRegByte(0,0x1D);//disable DAC power down
	WriteRegByte(0x24,0x1f);//select ext clk,mode=010,triangle=1
//	WriteRegByte(0x04,0x1f);//select ext clk,mode=010,triangle=0
	WriteRegByte(0,0x20);//to full-scale amplitude
//	WriteRegByte(0x60,0x20);//to full-scale amplitude.
//	WriteRegByte(0x40,0x20);//to full-scale amplitude.
	WriteReg(TW1,0x04,6);
	WriteReg(TW2,0x0a,6);
	WriteReg(DFW,0x10,6);
  	fbh=0;
	shk=1;
	UpdatePin=1;
	for(j=0;j<10;j++);
	UpdatePin=0;
/*	while(1)
	{
		shk=1;
		for(j=0;j<65535;j++);
		for(j=0;j<100;j++);
		shk=0;
		for(j=0;j<65535;j++);
		for(j=0;j<100;j++);
	}*/
}

void FmChipEx(void)
{
	unsigned char i;
	unsigned int j;
/*	TW1[5]=0x99;//sysclk=200MHz,freq=20M
	TW1[4]=0x99;
	TW1[3]=0x99;
	TW1[2]=0x99;
	TW1[1]=0x99;
	TW1[0]=0x19;
	TW1[5]=0x66;//sysclk=200MHz,freq=20M
	TW1[4]=0x66;
	TW1[3]=0x66;
	TW1[2]=0x66;
	TW1[1]=0x66;
	TW1[0]=0x26;

	TW2[5]=0x66;//freq=30M
	TW2[4]=0x66;
	TW2[3]=0x66;
	TW2[2]=0x66;
	TW2[1]=0x66;
	TW2[0]=0x26;
	

	//sysclk=200MHz,△freq=100kHz
	DFW[5]=0xe3;
	DFW[4]=0xa5;
	DFW[3]=0x9b;
	DFW[2]=0xc4;
	DFW[1]=0x20;
	DFW[0]=0x00;

//sysclk=200MHz,△freq=10kHz
	DFW[5]=0x63;
	DFW[4]=0x5d;
	DFW[3]=0xdc;
	DFW[2]=0x46;
	DFW[1]=0x03;
	DFW[0]=0x00;

	//sysclk=200MHz,ramp is 5.2ms
//	RampRC[2]=0xff;
	RampRC[2]=0x00;
	RampRC[1]=0xff;
//	RampRC[0]=0x0f;
	RampRC[0]=0x07;
	//sysclk=200MHz,upclk time is 43s
	UpdateClk[3]=0xff;
	UpdateClk[2]=0xff;
	UpdateClk[1]=0xff;
	UpdateClk[0]=0xff;


	//sysclk=200MHz,upclk time is 1s
	UpdateClk[3]=0xff;
	UpdateClk[2]=0xff;
	UpdateClk[1]=0xc0;
	UpdateClk[0]=0xfa;

	//sysclk=200MHz,upclk time is 0.1s
	UpdateClk[3]=0x80;
	UpdateClk[2]=0x96;
	UpdateClk[1]=0x98;
	UpdateClk[0]=0x00;

	//sysclk=200MHz,upclk time is 1s
	UpdateClk[3]=0x00;
	UpdateClk[2]=0xe1;
	UpdateClk[1]=0xf5;
	UpdateClk[0]=0x05;

	ShapeKI[1]=0xff;
	ShapeKI[0]=0xff;

	ShapeKQ[1]=0xff;
	ShapeKQ[0]=0xff;

	PhaseAd1[1]=0;
	PhaseAd1[0]=0;

	PhaseAd2[1]=0xff;
	PhaseAd2[0]=0xff;

	ShapeKR=0xff;*/

//	WriteRegByte(0x86,0x1f);//select ext clk,mode=011,CLRACC1=1
	WriteRegByte(0x87,0x1f);//select int clk,mode=011,CLRACC1=1
	WriteReg(UpdateClk,0x16,4);
	WriteReg(ShapeKI,0x21,2);
	WriteReg(ShapeKQ,0x23,2);
	WriteRegByte(ShapeKR,0x25);
//	WriteRegByte(0x60,0x20);//to full-scale amplitude.
	WriteRegByte(0x40,0x20);//to full-scale amplitude.
//	WriteRegByte(0x0,0x20);//to full-scale amplitude.

	WriteReg(TW1,0x04,6);
	WriteReg(TW2,0x0a,6);
	WriteReg(DFW,0x10,6);
	WriteReg(RampRC,0x1a,3);
	//Note:when fbh=0,select mark2
	//the fequency start at 0Hz,stop till it reach tw1;
	//when fbh=0,and select mark1,fequency start at 0Hz , increase till
	//it reach 10*MHz,then decrease to 0Hz,and disappear,then recurrence
	fbh=0;
	shk=1;
	UpdatePin=1;
	UpdatePin=0;
}



//daORadr select op for data or adress writen
void WriteRegByte(unsigned char da,unsigned char adr)
{

		unsigned char k;
	    wr=1;
		AdrOrData=adr<<2;
	    cpadr=1;
	    cpadr=0;

		AdrOrData=ConvDa(da);
	    cpdata=1;
	    cpdata=0;

		for(k=0;k<255;k++);
	    wr=0;       //operate read of DDS register
		for(k=0;k<255;k++);
	    wr=1;

}


void WriteReg(unsigned char *buff,unsigned char adr,unsigned char len)
{
	unsigned char i;
	unsigned char k;

	for(i=0;i<len;i++)
	{
		unsigned char da;
		wr=1;
		cpadr=0;
		AdrOrData=(adr++)<<2;
	    cpadr=1;
	    cpadr=0;
		cpdata=0;
		da=*buff;
		AdrOrData=ConvDa(da);
		buff++;
	    cpdata=1;
	    cpdata=0;
	    wr=0;       //operate read of DDS register
		for(k=0;k<255;k++);
	    wr=1;


	}
}
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