my_sram_timesim.vhd

FPGA系统的sram的软仿真设计

    generic map(
      INIT => X"BB88"
    )
    port map (
      ADR0 => data_6_5,
      ADR1 => Q_n0055,
      ADR2 => VCC,
      ADR3 => data_in_5_IBUF,
      O => Mmux_n0009_Result_5_1_O
    );
  Mmux_n0009_Result_4_1 : X_LUT4
    generic map(
      INIT => X"F5A0"
    )
    port map (
      ADR0 => Q_n0055,
      ADR1 => VCC,
      ADR2 => data_6_4,
      ADR3 => data_in_4_IBUF,
      O => Mmux_n0009_Result_4_1_O
    );
  Mmux_n0010_Result_1_1 : X_LUT4
    generic map(
      INIT => X"FC30"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Q_n0022,
      ADR2 => data_7_1,
      ADR3 => data_in_1_IBUF,
      O => Mmux_n0010_Result_1_1_O
    );
  Mmux_n0010_Result_0_1 : X_LUT4
    generic map(
      INIT => X"FC30"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Q_n0022,
      ADR2 => data_7_0,
      ADR3 => data_in_0_IBUF,
      O => Mmux_n0010_Result_0_1_O
    );
  Mmux_n0010_Result_3_1 : X_LUT4
    generic map(
      INIT => X"FC0C"
    )
    port map (
      ADR0 => VCC,
      ADR1 => data_7_3,
      ADR2 => Q_n0022,
      ADR3 => data_in_3_IBUF,
      O => Mmux_n0010_Result_3_1_O
    );
  Mmux_n0010_Result_2_1 : X_LUT4
    generic map(
      INIT => X"F0CC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => data_7_2,
      ADR2 => data_in_2_IBUF,
      ADR3 => Q_n0022,
      O => Mmux_n0010_Result_2_1_O
    );
  Mtridata_data_out_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_out_4_OD,
      CE => Q_n0038,
      CLK => clock_BUFGP,
      SET => GND,
      RST => data_out_4_OFF_RST,
      O => Mtridata_data_out(4)
    );
  data_out_4_OFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => data_out_4_OFF_RST
    );
  Mmux_n0010_Result_5_1 : X_LUT4
    generic map(
      INIT => X"FC30"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Q_n0022,
      ADR2 => data_7_5,
      ADR3 => data_in_5_IBUF,
      O => Mmux_n0010_Result_5_1_O
    );
  Mmux_n0010_Result_4_1 : X_LUT4
    generic map(
      INIT => X"EE22"
    )
    port map (
      ADR0 => data_7_4,
      ADR1 => Q_n0022,
      ADR2 => VCC,
      ADR3 => data_in_4_IBUF,
      O => Mmux_n0010_Result_4_1_O
    );
  Q_n00431 : X_LUT4
    generic map(
      INIT => X"FFFC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => waddr_1_IBUF,
      ADR2 => waddr_0_IBUF,
      ADR3 => waddr_2_IBUF,
      O => data_0_6_FROM
    );
  Mmux_n0003_Result_6_1 : X_LUT4
    generic map(
      INIT => X"CCF0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => data_0_6,
      ADR2 => data_in_6_IBUF,
      ADR3 => Q_n0043,
      O => Mmux_n0003_Result_6_1_O
    );
  data_0_6_XUSED : X_BUF
    port map (
      I => data_0_6_FROM,
      O => Q_n0043
    );
  Q_n00511 : X_LUT4
    generic map(
      INIT => X"FFDD"
    )
    port map (
      ADR0 => waddr_2_IBUF,
      ADR1 => waddr_1_IBUF,
      ADR2 => VCC,
      ADR3 => waddr_0_IBUF,
      O => data_4_6_FROM
    );
  Mmux_n0007_Result_6_1 : X_LUT4
    generic map(
      INIT => X"F0CC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => data_in_6_IBUF,
      ADR2 => data_4_6,
      ADR3 => Q_n0051,
      O => Mmux_n0007_Result_6_1_O
    );
  data_4_6_XUSED : X_BUF
    port map (
      I => data_4_6_FROM,
      O => Q_n0051
    );
  Q_n00451 : X_LUT4
    generic map(
      INIT => X"FAFF"
    )
    port map (
      ADR0 => waddr_1_IBUF,
      ADR1 => VCC,
      ADR2 => waddr_2_IBUF,
      ADR3 => waddr_0_IBUF,
      O => data_1_6_FROM
    );
  Mmux_n0004_Result_6_1 : X_LUT4
    generic map(
      INIT => X"CCF0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => data_1_6,
      ADR2 => data_in_6_IBUF,
      ADR3 => Q_n0045,
      O => Mmux_n0004_Result_6_1_O
    );
  data_1_6_XUSED : X_BUF
    port map (
      I => data_1_6_FROM,
      O => Q_n0045
    );
  Q_n00531 : X_LUT4
    generic map(
      INIT => X"F5FF"
    )
    port map (
      ADR0 => waddr_0_IBUF,
      ADR1 => VCC,
      ADR2 => waddr_1_IBUF,
      ADR3 => waddr_2_IBUF,
      O => data_5_6_FROM
    );
  Mmux_n0008_Result_6_1 : X_LUT4
    generic map(
      INIT => X"F0AA"
    )
    port map (
      ADR0 => data_in_6_IBUF,
      ADR1 => VCC,
      ADR2 => data_5_6,
      ADR3 => Q_n0053,
      O => Mmux_n0008_Result_6_1_O
    );
  data_5_6_XUSED : X_BUF
    port map (
      I => data_5_6_FROM,
      O => Q_n0053
    );
  Q_n00011 : X_LUT4
    generic map(
      INIT => X"00CC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => we_IBUF,
      ADR2 => VCC,
      ADR3 => re_IBUF,
      O => Q_n0001_FROM
    );
  Q_n00381 : X_LUT4
    generic map(
      INIT => X"F0FF"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => re_IBUF,
      ADR3 => we_IBUF,
      O => Q_n0001_GROM
    );
  Q_n0001_XUSED : X_BUF
    port map (
      I => Q_n0001_FROM,
      O => Q_n0001
    );
  Q_n0001_YUSED : X_BUF
    port map (
      I => Q_n0001_GROM,
      O => Q_n0038
    );
  Q_n00471 : X_LUT4
    generic map(
      INIT => X"FDFD"
    )
    port map (
      ADR0 => waddr_1_IBUF,
      ADR1 => waddr_2_IBUF,
      ADR2 => waddr_0_IBUF,
      ADR3 => VCC,
      O => data_2_6_FROM
    );
  Mmux_n0005_Result_6_1 : X_LUT4
    generic map(
      INIT => X"CCF0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => data_2_6,
      ADR2 => data_in_6_IBUF,
      ADR3 => Q_n0047,
      O => Mmux_n0005_Result_6_1_O
    );
  data_2_6_XUSED : X_BUF
    port map (
      I => data_2_6_FROM,
      O => Q_n0047
    );
  Q_n00551 : X_LUT4
    generic map(
      INIT => X"AFFF"
    )
    port map (
      ADR0 => waddr_0_IBUF,
      ADR1 => VCC,
      ADR2 => waddr_1_IBUF,
      ADR3 => waddr_2_IBUF,
      O => data_6_6_FROM
    );
  Mmux_n0009_Result_6_1 : X_LUT4
    generic map(
      INIT => X"CCF0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => data_6_6,
      ADR2 => data_in_6_IBUF,
      ADR3 => Q_n0055,
      O => Mmux_n0009_Result_6_1_O
    );
  data_6_6_XUSED : X_BUF
    port map (
      I => data_6_6_FROM,
      O => Q_n0055
    );
  Q_n00491 : X_LUT4
    generic map(
      INIT => X"FF5F"
    )
    port map (
      ADR0 => waddr_1_IBUF,
      ADR1 => VCC,
      ADR2 => waddr_0_IBUF,
      ADR3 => waddr_2_IBUF,
      O => data_3_6_FROM
    );
  Mmux_n0006_Result_6_1 : X_LUT4
    generic map(
      INIT => X"F0CC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => data_in_6_IBUF,
      ADR2 => data_3_6,
      ADR3 => Q_n0049,
      O => Mmux_n0006_Result_6_1_O
    );
  data_3_6_XUSED : X_BUF
    port map (
      I => data_3_6_FROM,
      O => Q_n0049
    );
  Q_n00121 : X_LUT4
    generic map(
      INIT => X"FF55"
    )
    port map (
      ADR0 => re_IBUF,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => we_IBUF,
      O => Q_n0012_GROM
    );
  Q_n0012_YUSED : X_BUF
    port map (
      I => Q_n0012_GROM,
      O => Q_n0012
    );
  Q_n00221 : X_LUT4
    generic map(
      INIT => X"8080"
    )
    port map (
      ADR0 => waddr_0_IBUF,
      ADR1 => waddr_2_IBUF,
      ADR2 => waddr_1_IBUF,
      ADR3 => VCC,
      O => data_7_6_FROM
    );
  Mmux_n0010_Result_6_1 : X_LUT4
    generic map(
      INIT => X"AAF0"
    )
    port map (
      ADR0 => data_in_6_IBUF,
      ADR1 => VCC,
      ADR2 => data_7_6,
      ADR3 => Q_n0022,
      O => Mmux_n0010_Result_6_1_O
    );
  data_7_6_XUSED : X_BUF
    port map (
      I => data_7_6_FROM,
      O => Q_n0022
    );
  Mtrien_data_out_5_52 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0012,
      CE => Q_n0038,
      CLK => clock_BUFGP,
      SET => GND,
      RST => data_out_3_TFF_RST,
      O => Mtrien_data_out_4
    );
  data_out_3_TFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => data_out_3_TFF_RST
    );
  Mtrien_data_out_4_53 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0012,
      CE => Q_n0038,
      CLK => clock_BUFGP,
      SET => GND,
      RST => data_out_4_TFF_RST,
      O => Mtrien_data_out_3
    );
  data_out_4_TFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => data_out_4_TFF_RST
    );
  data_2_3_54 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Mmux_n0005_Result_3_1_O,
      CE => Q_n0001,
      CLK => clock_BUFGP,
      SET => GND,
      RST => data_2_3_FFX_RST,
      O => data_2_3
    );
  data_2_3_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => data_2_3_FFX_RST
    );
  data_6_7_55 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Mmux_n0009_Result_7_1_O,
      CE => Q_n0001,
      CLK => clock_BUFGP,
      SET => GND,
      RST => data_6_7_FFX_RST,
      O => data_6_7
    );
  data_6_7_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => data_6_7_FFX_RST
    );
  data_1_7_56 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Mmux_n0004_Result_7_1_O,
      CE => Q_n0001,
      CLK => clock_BUFGP,
      SET => GND,
      RST => data_6_7_FFY_RST,
      O => data_1_7
    );
  data_6_7_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => data_6_7_FFY_RST
    );
  data_2_5_57 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Mmux_n0005_Result_5_1_O,
      CE => Q_n0001,
      CLK => clock_BUFGP,
      SET => GND,
      RST => data_2_5_FFX_RST,
      O => data_2_5
    );
  data_2_5_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => data_2_5_FFX_RST
    );
  data_2_4_58 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Mmux_n0005_Result_4_1_O,
      CE => Q_n0001,
      CLK => clock_BUFGP,
      SET => GND,
      RST => data_2_5_FFY_RST,
      O => data_2_4
    );
  data_2_5_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => data_2_5_FFY_RST
    );
  data_3_1_59 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Mmux_n0006_Result_1_1_O,
      CE => Q_n0001,
      CLK => clock_BUFGP,
      SET => GND,
      RST => data_3_1_FFX_RST,
      O => data_3_1
    );
  data_3_1_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => data_3_1_FFX_RST
    );
  data_3_0_60 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Mmux_n0006_Result_0_1_O,
      CE => Q_n0001,
      CLK => clock_BUFGP,
      SET => GND,
      RST => data_3_1_FFY_RST,
      O => data_3_0
    );
  data_3_1_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => data_3_1_FFY_RST
    );
  data_3_3_61 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Mmux_n0006_Result_3_1_O,
      CE => Q_n0001,
      CLK => clock_BUFGP,
      SET => GND,
      RST => data_3_3_FFX_RST,
      O => data_3_3
    );
  data_3_3_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => data_3_3_FFX_RST
    );
  data_3_2_62 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Mmux_n0006_Result_2_1_O,
      CE => Q_n0001,
      CLK => clock_BUFGP,
      SE