my_sram_timesim.vhd

FPGA系统的sram的软仿真设计

    port map (
      ADR0 => data_in_7_IBUF,
      ADR1 => VCC,
      ADR2 => data_7_7,
      ADR3 => Q_n0022,
      O => Mmux_n0010_Result_7_1_O
    );
  Mmux_n0003_Result_7_1 : X_LUT4
    generic map(
      INIT => X"FC30"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Q_n0043,
      ADR2 => data_in_7_IBUF,
      ADR3 => data_0_7,
      O => Mmux_n0003_Result_7_1_O
    );
  data_1_5_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => data_1_5_FFY_RST
    );
  data_1_4_46 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Mmux_n0004_Result_4_1_O,
      CE => Q_n0001,
      CLK => clock_BUFGP,
      SET => GND,
      RST => data_1_5_FFY_RST,
      O => data_1_4
    );
  data_1_5_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => data_1_5_FFX_RST
    );
  data_1_5_47 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Mmux_n0004_Result_5_1_O,
      CE => Q_n0001,
      CLK => clock_BUFGP,
      SET => GND,
      RST => data_1_5_FFX_RST,
      O => data_1_5
    );
  Mmux_n0004_Result_5_1 : X_LUT4
    generic map(
      INIT => X"CFC0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => data_1_5,
      ADR2 => Q_n0045,
      ADR3 => data_in_5_IBUF,
      O => Mmux_n0004_Result_5_1_O
    );
  Mmux_n0004_Result_4_1 : X_LUT4
    generic map(
      INIT => X"F5A0"
    )
    port map (
      ADR0 => Q_n0045,
      ADR1 => VCC,
      ADR2 => data_1_4,
      ADR3 => data_in_4_IBUF,
      O => Mmux_n0004_Result_4_1_O
    );
  Mtridata_data_out_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_out_2_OD,
      CE => Q_n0038,
      CLK => clock_BUFGP,
      SET => GND,
      RST => data_out_2_OFF_RST,
      O => Mtridata_data_out(2)
    );
  data_out_2_OFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => data_out_2_OFF_RST
    );
  data_2_1_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => data_2_1_FFY_RST
    );
  data_2_0_48 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Mmux_n0005_Result_0_1_O,
      CE => Q_n0001,
      CLK => clock_BUFGP,
      SET => GND,
      RST => data_2_1_FFY_RST,
      O => data_2_0
    );
  data_2_1_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => data_2_1_FFX_RST
    );
  data_2_1_49 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Mmux_n0005_Result_1_1_O,
      CE => Q_n0001,
      CLK => clock_BUFGP,
      SET => GND,
      RST => data_2_1_FFX_RST,
      O => data_2_1
    );
  Mmux_n0005_Result_1_1 : X_LUT4
    generic map(
      INIT => X"CFC0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => data_2_1,
      ADR2 => Q_n0047,
      ADR3 => data_in_1_IBUF,
      O => Mmux_n0005_Result_1_1_O
    );
  Mmux_n0005_Result_0_1 : X_LUT4
    generic map(
      INIT => X"FC30"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Q_n0047,
      ADR2 => data_in_0_IBUF,
      ADR3 => data_2_0,
      O => Mmux_n0005_Result_0_1_O
    );
  data_2_3_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => data_2_3_FFY_RST
    );
  data_2_2_50 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Mmux_n0005_Result_2_1_O,
      CE => Q_n0001,
      CLK => clock_BUFGP,
      SET => GND,
      RST => data_2_3_FFY_RST,
      O => data_2_2
    );
  Mmux_n0005_Result_3_1 : X_LUT4
    generic map(
      INIT => X"E4E4"
    )
    port map (
      ADR0 => Q_n0047,
      ADR1 => data_in_3_IBUF,
      ADR2 => data_2_3,
      ADR3 => VCC,
      O => Mmux_n0005_Result_3_1_O
    );
  Mmux_n0005_Result_2_1 : X_LUT4
    generic map(
      INIT => X"FC30"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Q_n0047,
      ADR2 => data_in_2_IBUF,
      ADR3 => data_2_2,
      O => Mmux_n0005_Result_2_1_O
    );
  Mmux_n0009_Result_7_1 : X_LUT4
    generic map(
      INIT => X"DD88"
    )
    port map (
      ADR0 => Q_n0055,
      ADR1 => data_6_7,
      ADR2 => VCC,
      ADR3 => data_in_7_IBUF,
      O => Mmux_n0009_Result_7_1_O
    );
  Mmux_n0004_Result_7_1 : X_LUT4
    generic map(
      INIT => X"F3C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Q_n0045,
      ADR2 => data_1_7,
      ADR3 => data_in_7_IBUF,
      O => Mmux_n0004_Result_7_1_O
    );
  Mmux_n0005_Result_5_1 : X_LUT4
    generic map(
      INIT => X"EE22"
    )
    port map (
      ADR0 => data_in_5_IBUF,
      ADR1 => Q_n0047,
      ADR2 => VCC,
      ADR3 => data_2_5,
      O => Mmux_n0005_Result_5_1_O
    );
  Mmux_n0005_Result_4_1 : X_LUT4
    generic map(
      INIT => X"FA50"
    )
    port map (
      ADR0 => Q_n0047,
      ADR1 => VCC,
      ADR2 => data_in_4_IBUF,
      ADR3 => data_2_4,
      O => Mmux_n0005_Result_4_1_O
    );
  Mmux_n0006_Result_1_1 : X_LUT4
    generic map(
      INIT => X"F0CC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => data_in_1_IBUF,
      ADR2 => data_3_1,
      ADR3 => Q_n0049,
      O => Mmux_n0006_Result_1_1_O
    );
  Mmux_n0006_Result_0_1 : X_LUT4
    generic map(
      INIT => X"FC30"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Q_n0049,
      ADR2 => data_in_0_IBUF,
      ADR3 => data_3_0,
      O => Mmux_n0006_Result_0_1_O
    );
  Mmux_n0006_Result_3_1 : X_LUT4
    generic map(
      INIT => X"DD88"
    )
    port map (
      ADR0 => Q_n0049,
      ADR1 => data_3_3,
      ADR2 => VCC,
      ADR3 => data_in_3_IBUF,
      O => Mmux_n0006_Result_3_1_O
    );
  Mmux_n0006_Result_2_1 : X_LUT4
    generic map(
      INIT => X"FA50"
    )
    port map (
      ADR0 => Q_n0049,
      ADR1 => VCC,
      ADR2 => data_in_2_IBUF,
      ADR3 => data_3_2,
      O => Mmux_n0006_Result_2_1_O
    );
  Mmux_n0008_Result_7_1 : X_LUT4
    generic map(
      INIT => X"FA0A"
    )
    port map (
      ADR0 => data_in_7_IBUF,
      ADR1 => VCC,
      ADR2 => Q_n0053,
      ADR3 => data_5_7,
      O => Mmux_n0008_Result_7_1_O
    );
  Mmux_n0005_Result_7_1 : X_LUT4
    generic map(
      INIT => X"B8B8"
    )
    port map (
      ADR0 => data_2_7,
      ADR1 => Q_n0047,
      ADR2 => data_in_7_IBUF,
      ADR3 => VCC,
      O => Mmux_n0005_Result_7_1_O
    );
  Mmux_n0006_Result_5_1 : X_LUT4
    generic map(
      INIT => X"CACA"
    )
    port map (
      ADR0 => data_in_5_IBUF,
      ADR1 => data_3_5,
      ADR2 => Q_n0049,
      ADR3 => VCC,
      O => Mmux_n0006_Result_5_1_O
    );
  Mmux_n0006_Result_4_1 : X_LUT4
    generic map(
      INIT => X"CFC0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => data_3_4,
      ADR2 => Q_n0049,
      ADR3 => data_in_4_IBUF,
      O => Mmux_n0006_Result_4_1_O
    );
  Mmux_n0007_Result_1_1 : X_LUT4
    generic map(
      INIT => X"F0AA"
    )
    port map (
      ADR0 => data_in_1_IBUF,
      ADR1 => VCC,
      ADR2 => data_4_1,
      ADR3 => Q_n0051,
      O => Mmux_n0007_Result_1_1_O
    );
  Mmux_n0007_Result_0_1 : X_LUT4
    generic map(
      INIT => X"CFC0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => data_4_0,
      ADR2 => Q_n0051,
      ADR3 => data_in_0_IBUF,
      O => Mmux_n0007_Result_0_1_O
    );
  Mmux_n0007_Result_3_1 : X_LUT4
    generic map(
      INIT => X"F0CC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => data_in_3_IBUF,
      ADR2 => data_4_3,
      ADR3 => Q_n0051,
      O => Mmux_n0007_Result_3_1_O
    );
  Mmux_n0007_Result_2_1 : X_LUT4
    generic map(
      INIT => X"FC30"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Q_n0051,
      ADR2 => data_in_2_IBUF,
      ADR3 => data_4_2,
      O => Mmux_n0007_Result_2_1_O
    );
  Mmux_n0007_Result_7_1 : X_LUT4
    generic map(
      INIT => X"F0CC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => data_in_7_IBUF,
      ADR2 => data_4_7,
      ADR3 => Q_n0051,
      O => Mmux_n0007_Result_7_1_O
    );
  Mmux_n0006_Result_7_1 : X_LUT4
    generic map(
      INIT => X"F3C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Q_n0049,
      ADR2 => data_3_7,
      ADR3 => data_in_7_IBUF,
      O => Mmux_n0006_Result_7_1_O
    );
  Mmux_n0007_Result_5_1 : X_LUT4
    generic map(
      INIT => X"CACA"
    )
    port map (
      ADR0 => data_in_5_IBUF,
      ADR1 => data_4_5,
      ADR2 => Q_n0051,
      ADR3 => VCC,
      O => Mmux_n0007_Result_5_1_O
    );
  Mmux_n0007_Result_4_1 : X_LUT4
    generic map(
      INIT => X"FA50"
    )
    port map (
      ADR0 => Q_n0051,
      ADR1 => VCC,
      ADR2 => data_in_4_IBUF,
      ADR3 => data_4_4,
      O => Mmux_n0007_Result_4_1_O
    );
  Mtrien_data_out_6_51 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0012,
      CE => Q_n0038,
      CLK => clock_BUFGP,
      SET => GND,
      RST => data_out_2_TFF_RST,
      O => Mtrien_data_out_5
    );
  data_out_2_TFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => data_out_2_TFF_RST
    );
  Mmux_n0008_Result_1_1 : X_LUT4
    generic map(
      INIT => X"FC0C"
    )
    port map (
      ADR0 => VCC,
      ADR1 => data_in_1_IBUF,
      ADR2 => Q_n0053,
      ADR3 => data_5_1,
      O => Mmux_n0008_Result_1_1_O
    );
  Mmux_n0008_Result_0_1 : X_LUT4
    generic map(
      INIT => X"FC0C"
    )
    port map (
      ADR0 => VCC,
      ADR1 => data_in_0_IBUF,
      ADR2 => Q_n0053,
      ADR3 => data_5_0,
      O => Mmux_n0008_Result_0_1_O
    );
  Mtridata_data_out_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_out_3_OD,
      CE => Q_n0038,
      CLK => clock_BUFGP,
      SET => GND,
      RST => data_out_3_OFF_RST,
      O => Mtridata_data_out(3)
    );
  data_out_3_OFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => data_out_3_OFF_RST
    );
  Mmux_n0008_Result_3_1 : X_LUT4
    generic map(
      INIT => X"E4E4"
    )
    port map (
      ADR0 => Q_n0053,
      ADR1 => data_in_3_IBUF,
      ADR2 => data_5_3,
      ADR3 => VCC,
      O => Mmux_n0008_Result_3_1_O
    );
  Mmux_n0008_Result_2_1 : X_LUT4
    generic map(
      INIT => X"FC0C"
    )
    port map (
      ADR0 => VCC,
      ADR1 => data_in_2_IBUF,
      ADR2 => Q_n0053,
      ADR3 => data_5_2,
      O => Mmux_n0008_Result_2_1_O
    );
  Mmux_n0008_Result_5_1 : X_LUT4
    generic map(
      INIT => X"CACA"
    )
    port map (
      ADR0 => data_in_5_IBUF,
      ADR1 => data_5_5,
      ADR2 => Q_n0053,
      ADR3 => VCC,
      O => Mmux_n0008_Result_5_1_O
    );
  Mmux_n0008_Result_4_1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => Q_n0053,
      ADR1 => data_5_4,
      ADR2 => data_in_4_IBUF,
      ADR3 => VCC,
      O => Mmux_n0008_Result_4_1_O
    );
  Mmux_n0009_Result_1_1 : X_LUT4
    generic map(
      INIT => X"FA0A"
    )
    port map (
      ADR0 => data_in_1_IBUF,
      ADR1 => VCC,
      ADR2 => Q_n0055,
      ADR3 => data_6_1,
      O => Mmux_n0009_Result_1_1_O
    );
  Mmux_n0009_Result_0_1 : X_LUT4
    generic map(
      INIT => X"CCF0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => data_6_0,
      ADR2 => data_in_0_IBUF,
      ADR3 => Q_n0055,
      O => Mmux_n0009_Result_0_1_O
    );
  Mmux_n0009_Result_3_1 : X_LUT4
    generic map(
      INIT => X"CCAA"
    )
    port map (
      ADR0 => data_in_3_IBUF,
      ADR1 => data_6_3,
      ADR2 => VCC,
      ADR3 => Q_n0055,
      O => Mmux_n0009_Result_3_1_O
    );
  Mmux_n0009_Result_2_1 : X_LUT4
    generic map(
      INIT => X"AFA0"
    )
    port map (
      ADR0 => data_6_2,
      ADR1 => VCC,
      ADR2 => Q_n0055,
      ADR3 => data_in_2_IBUF,
      O => Mmux_n0009_Result_2_1_O
    );
  Mmux_n0009_Result_5_1 : X_LUT4