my_sram_timesim.vhd

FPGA系统的sram的软仿真设计

    );
  Mmux_n0011_inst_lut3_151 : X_LUT4
    generic map(
      INIT => X"DD88"
    )
    port map (
      ADR0 => raddr_0_IBUF,
      ADR1 => data_7_3,
      ADR2 => VCC,
      ADR3 => data_6_3,
      O => Mmux_n0011_inst_lut3_151_O
    );
  Mmux_n0011_inst_lut3_141 : X_LUT4
    generic map(
      INIT => X"AAF0"
    )
    port map (
      ADR0 => data_5_3,
      ADR1 => VCC,
      ADR2 => data_4_3,
      ADR3 => raddr_0_IBUF,
      O => Mmux_n0011_inst_lut3_141_O
    );
  Q_n0011_3_YUSED : X_BUF
    port map (
      I => Q_n0011_3_F6MUX,
      O => Q_n0011(3)
    );
  Mmux_n0011_inst_mux_f6_3 : X_MUX2
    port map (
      IA => Mmux_n0011_net23,
      IB => Mmux_n0011_net26,
      SEL => raddr_2_IBUF,
      O => Q_n0011_3_F6MUX
    );
  Mmux_n0011_inst_mux_f5_8 : X_MUX2
    port map (
      IA => Mmux_n0011_inst_lut3_161_O,
      IB => Mmux_n0011_inst_lut3_171_O,
      SEL => raddr_1_IBUF,
      O => Mmux_n0011_net30_F5MUX
    );
  Mmux_n0011_inst_lut3_171 : X_LUT4
    generic map(
      INIT => X"CFC0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => data_3_4,
      ADR2 => raddr_0_IBUF,
      ADR3 => data_2_4,
      O => Mmux_n0011_inst_lut3_171_O
    );
  Mmux_n0011_inst_lut3_161 : X_LUT4
    generic map(
      INIT => X"AFA0"
    )
    port map (
      ADR0 => data_1_4,
      ADR1 => VCC,
      ADR2 => raddr_0_IBUF,
      ADR3 => data_0_4,
      O => Mmux_n0011_inst_lut3_161_O
    );
  Mmux_n0011_net30_F5USED : X_BUF
    port map (
      I => Mmux_n0011_net30_F5MUX,
      O => Mmux_n0011_net30
    );
  Mmux_n0011_inst_mux_f5_9 : X_MUX2
    port map (
      IA => Mmux_n0011_inst_lut3_181_O,
      IB => Mmux_n0011_inst_lut3_191_O,
      SEL => raddr_1_IBUF,
      O => Mmux_n0011_net33
    );
  Mmux_n0011_inst_lut3_191 : X_LUT4
    generic map(
      INIT => X"ACAC"
    )
    port map (
      ADR0 => data_7_4,
      ADR1 => data_6_4,
      ADR2 => raddr_0_IBUF,
      ADR3 => VCC,
      O => Mmux_n0011_inst_lut3_191_O
    );
  Mmux_n0011_inst_lut3_181 : X_LUT4
    generic map(
      INIT => X"FC30"
    )
    port map (
      ADR0 => VCC,
      ADR1 => raddr_0_IBUF,
      ADR2 => data_4_4,
      ADR3 => data_5_4,
      O => Mmux_n0011_inst_lut3_181_O
    );
  Q_n0011_4_YUSED : X_BUF
    port map (
      I => Q_n0011_4_F6MUX,
      O => Q_n0011(4)
    );
  Mmux_n0011_inst_mux_f6_4 : X_MUX2
    port map (
      IA => Mmux_n0011_net30,
      IB => Mmux_n0011_net33,
      SEL => raddr_2_IBUF,
      O => Q_n0011_4_F6MUX
    );
  Mmux_n0011_inst_mux_f5_10 : X_MUX2
    port map (
      IA => Mmux_n0011_inst_lut3_201_O,
      IB => Mmux_n0011_inst_lut3_211_O,
      SEL => raddr_1_IBUF,
      O => Mmux_n0011_net37_F5MUX
    );
  Mmux_n0011_inst_lut3_211 : X_LUT4
    generic map(
      INIT => X"DD88"
    )
    port map (
      ADR0 => raddr_0_IBUF,
      ADR1 => data_3_5,
      ADR2 => VCC,
      ADR3 => data_2_5,
      O => Mmux_n0011_inst_lut3_211_O
    );
  Mmux_n0011_inst_lut3_201 : X_LUT4
    generic map(
      INIT => X"EE44"
    )
    port map (
      ADR0 => raddr_0_IBUF,
      ADR1 => data_0_5,
      ADR2 => VCC,
      ADR3 => data_1_5,
      O => Mmux_n0011_inst_lut3_201_O
    );
  Mmux_n0011_net37_F5USED : X_BUF
    port map (
      I => Mmux_n0011_net37_F5MUX,
      O => Mmux_n0011_net37
    );
  Mmux_n0011_inst_mux_f5_11 : X_MUX2
    port map (
      IA => Mmux_n0011_inst_lut3_221_O,
      IB => Mmux_n0011_inst_lut3_231_O,
      SEL => raddr_1_IBUF,
      O => Mmux_n0011_net40
    );
  Mmux_n0011_inst_lut3_231 : X_LUT4
    generic map(
      INIT => X"CCAA"
    )
    port map (
      ADR0 => data_6_5,
      ADR1 => data_7_5,
      ADR2 => VCC,
      ADR3 => raddr_0_IBUF,
      O => Mmux_n0011_inst_lut3_231_O
    );
  Mmux_n0011_inst_lut3_221 : X_LUT4
    generic map(
      INIT => X"AAF0"
    )
    port map (
      ADR0 => data_5_5,
      ADR1 => VCC,
      ADR2 => data_4_5,
      ADR3 => raddr_0_IBUF,
      O => Mmux_n0011_inst_lut3_221_O
    );
  Q_n0011_5_YUSED : X_BUF
    port map (
      I => Q_n0011_5_F6MUX,
      O => Q_n0011(5)
    );
  Mmux_n0011_inst_mux_f6_5 : X_MUX2
    port map (
      IA => Mmux_n0011_net37,
      IB => Mmux_n0011_net40,
      SEL => raddr_2_IBUF,
      O => Q_n0011_5_F6MUX
    );
  Mtrien_data_out_7 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0012,
      CE => Q_n0038,
      CLK => clock_BUFGP,
      SET => GND,
      RST => data_out_1_TFF_RST,
      O => Mtrien_data_out_6
    );
  data_out_1_TFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => data_out_1_TFF_RST
    );
  Mmux_n0011_inst_mux_f5_12 : X_MUX2
    port map (
      IA => Mmux_n0011_inst_lut3_241_O,
      IB => Mmux_n0011_inst_lut3_251_O,
      SEL => raddr_1_IBUF,
      O => Mmux_n0011_net44_F5MUX
    );
  Mmux_n0011_inst_lut3_251 : X_LUT4
    generic map(
      INIT => X"CCAA"
    )
    port map (
      ADR0 => data_2_6,
      ADR1 => data_3_6,
      ADR2 => VCC,
      ADR3 => raddr_0_IBUF,
      O => Mmux_n0011_inst_lut3_251_O
    );
  Mmux_n0011_inst_lut3_241 : X_LUT4
    generic map(
      INIT => X"FA0A"
    )
    port map (
      ADR0 => data_0_6,
      ADR1 => VCC,
      ADR2 => raddr_0_IBUF,
      ADR3 => data_1_6,
      O => Mmux_n0011_inst_lut3_241_O
    );
  Mmux_n0011_net44_F5USED : X_BUF
    port map (
      I => Mmux_n0011_net44_F5MUX,
      O => Mmux_n0011_net44
    );
  Mmux_n0011_inst_mux_f5_13 : X_MUX2
    port map (
      IA => Mmux_n0011_inst_lut3_261_O,
      IB => Mmux_n0011_inst_lut3_271_O,
      SEL => raddr_1_IBUF,
      O => Mmux_n0011_net47
    );
  Mmux_n0011_inst_lut3_271 : X_LUT4
    generic map(
      INIT => X"CCAA"
    )
    port map (
      ADR0 => data_6_6,
      ADR1 => data_7_6,
      ADR2 => VCC,
      ADR3 => raddr_0_IBUF,
      O => Mmux_n0011_inst_lut3_271_O
    );
  Mmux_n0011_inst_lut3_261 : X_LUT4
    generic map(
      INIT => X"FA50"
    )
    port map (
      ADR0 => raddr_0_IBUF,
      ADR1 => VCC,
      ADR2 => data_4_6,
      ADR3 => data_5_6,
      O => Mmux_n0011_inst_lut3_261_O
    );
  Q_n0011_6_YUSED : X_BUF
    port map (
      I => Q_n0011_6_F6MUX,
      O => Q_n0011(6)
    );
  Mmux_n0011_inst_mux_f6_6 : X_MUX2
    port map (
      IA => Mmux_n0011_net44,
      IB => Mmux_n0011_net47,
      SEL => raddr_2_IBUF,
      O => Q_n0011_6_F6MUX
    );
  Mmux_n0011_inst_mux_f5_14 : X_MUX2
    port map (
      IA => Mmux_n0011_inst_lut3_281_O,
      IB => Mmux_n0011_inst_lut3_291_O,
      SEL => raddr_1_IBUF,
      O => Mmux_n0011_net51_F5MUX
    );
  Mmux_n0011_inst_lut3_291 : X_LUT4
    generic map(
      INIT => X"B8B8"
    )
    port map (
      ADR0 => data_3_7,
      ADR1 => raddr_0_IBUF,
      ADR2 => data_2_7,
      ADR3 => VCC,
      O => Mmux_n0011_inst_lut3_291_O
    );
  Mmux_n0011_inst_lut3_281 : X_LUT4
    generic map(
      INIT => X"F5A0"
    )
    port map (
      ADR0 => raddr_0_IBUF,
      ADR1 => VCC,
      ADR2 => data_1_7,
      ADR3 => data_0_7,
      O => Mmux_n0011_inst_lut3_281_O
    );
  Mmux_n0011_net51_F5USED : X_BUF
    port map (
      I => Mmux_n0011_net51_F5MUX,
      O => Mmux_n0011_net51
    );
  Mmux_n0011_inst_mux_f5_15 : X_MUX2
    port map (
      IA => Mmux_n0011_inst_lut3_301_O,
      IB => Mmux_n0011_inst_lut3_311_O,
      SEL => raddr_1_IBUF,
      O => Mmux_n0011_net54
    );
  Mmux_n0011_inst_lut3_311 : X_LUT4
    generic map(
      INIT => X"AACC"
    )
    port map (
      ADR0 => data_7_7,
      ADR1 => data_6_7,
      ADR2 => VCC,
      ADR3 => raddr_0_IBUF,
      O => Mmux_n0011_inst_lut3_311_O
    );
  Mmux_n0011_inst_lut3_301 : X_LUT4
    generic map(
      INIT => X"FC30"
    )
    port map (
      ADR0 => VCC,
      ADR1 => raddr_0_IBUF,
      ADR2 => data_4_7,
      ADR3 => data_5_7,
      O => Mmux_n0011_inst_lut3_301_O
    );
  Q_n0011_7_YUSED : X_BUF
    port map (
      I => Q_n0011_7_F6MUX,
      O => Q_n0011(7)
    );
  Mmux_n0011_inst_mux_f6_7 : X_MUX2
    port map (
      IA => Mmux_n0011_net51,
      IB => Mmux_n0011_net54,
      SEL => raddr_2_IBUF,
      O => Q_n0011_7_F6MUX
    );
  Mmux_n0003_Result_1_1 : X_LUT4
    generic map(
      INIT => X"FC30"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Q_n0043,
      ADR2 => data_in_1_IBUF,
      ADR3 => data_0_1,
      O => Mmux_n0003_Result_1_1_O
    );
  Mmux_n0003_Result_0_1 : X_LUT4
    generic map(
      INIT => X"F3C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Q_n0043,
      ADR2 => data_0_0,
      ADR3 => data_in_0_IBUF,
      O => Mmux_n0003_Result_0_1_O
    );
  Mmux_n0003_Result_3_1 : X_LUT4
    generic map(
      INIT => X"FC0C"
    )
    port map (
      ADR0 => VCC,
      ADR1 => data_in_3_IBUF,
      ADR2 => Q_n0043,
      ADR3 => data_0_3,
      O => Mmux_n0003_Result_3_1_O
    );
  Mmux_n0003_Result_2_1 : X_LUT4
    generic map(
      INIT => X"FA50"
    )
    port map (
      ADR0 => Q_n0043,
      ADR1 => VCC,
      ADR2 => data_in_2_IBUF,
      ADR3 => data_0_2,
      O => Mmux_n0003_Result_2_1_O
    );
  Mmux_n0003_Result_5_1 : X_LUT4
    generic map(
      INIT => X"FA0A"
    )
    port map (
      ADR0 => data_in_5_IBUF,
      ADR1 => VCC,
      ADR2 => Q_n0043,
      ADR3 => data_0_5,
      O => Mmux_n0003_Result_5_1_O
    );
  Mmux_n0003_Result_4_1 : X_LUT4
    generic map(
      INIT => X"FA50"
    )
    port map (
      ADR0 => Q_n0043,
      ADR1 => VCC,
      ADR2 => data_in_4_IBUF,
      ADR3 => data_0_4,
      O => Mmux_n0003_Result_4_1_O
    );
  data_1_1_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => data_1_1_FFX_RST
    );
  data_1_1_41 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Mmux_n0004_Result_1_1_O,
      CE => Q_n0001,
      CLK => clock_BUFGP,
      SET => GND,
      RST => data_1_1_FFX_RST,
      O => data_1_1
    );
  Mmux_n0004_Result_1_1 : X_LUT4
    generic map(
      INIT => X"CCF0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => data_1_1,
      ADR2 => data_in_1_IBUF,
      ADR3 => Q_n0045,
      O => Mmux_n0004_Result_1_1_O
    );
  Mmux_n0004_Result_0_1 : X_LUT4
    generic map(
      INIT => X"FA0A"
    )
    port map (
      ADR0 => data_in_0_IBUF,
      ADR1 => VCC,
      ADR2 => Q_n0045,
      ADR3 => data_1_0,
      O => Mmux_n0004_Result_0_1_O
    );
  data_1_3_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => data_1_3_FFY_RST
    );
  data_1_2_42 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Mmux_n0004_Result_2_1_O,
      CE => Q_n0001,
      CLK => clock_BUFGP,
      SET => GND,
      RST => data_1_3_FFY_RST,
      O => data_1_2
    );
  data_1_3_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => data_1_3_FFX_RST
    );
  data_1_3_43 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Mmux_n0004_Result_3_1_O,
      CE => Q_n0001,
      CLK => clock_BUFGP,
      SET => GND,
      RST => data_1_3_FFX_RST,
      O => data_1_3
    );
  Mmux_n0004_Result_3_1 : X_LUT4
    generic map(
      INIT => X"F5A0"
    )
    port map (
      ADR0 => Q_n0045,
      ADR1 => VCC,
      ADR2 => data_1_3,
      ADR3 => data_in_3_IBUF,
      O => Mmux_n0004_Result_3_1_O
    );
  Mmux_n0004_Result_2_1 : X_LUT4
    generic map(
      INIT => X"FA0A"
    )
    port map (
      ADR0 => data_in_2_IBUF,
      ADR1 => VCC,
      ADR2 => Q_n0045,
      ADR3 => data_1_2,
      O => Mmux_n0004_Result_2_1_O
    );
  data_7_7_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => data_7_7_FFY_RST
    );
  data_0_7_44 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Mmux_n0003_Result_7_1_O,
      CE => Q_n0001,
      CLK => clock_BUFGP,
      SET => GND,
      RST => data_7_7_FFY_RST,
      O => data_0_7
    );
  data_7_7_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => data_7_7_FFX_RST
    );
  data_7_7_45 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Mmux_n0010_Result_7_1_O,
      CE => Q_n0001,
      CLK => clock_BUFGP,
      SET => GND,
      RST => data_7_7_FFX_RST,
      O => data_7_7
    );
  Mmux_n0010_Result_7_1 : X_LUT4
    generic map(
      INIT => X"AAF0"
    )