my_sram_timesim.vhd

FPGA系统的sram的软仿真设计

      CTL => data_out_2_ENABLE,
      O => data_out(2)
    );
  data_out_2_ENABLEINV : X_INV
    port map (
      I => data_out_2_TORGTS,
      O => data_out_2_ENABLE
    );
  data_out_2_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => Mtrien_data_out_5,
      O => data_out_2_TORGTS
    );
  data_out_2_OUTMUX_23 : X_BUF
    port map (
      I => Mtridata_data_out(2),
      O => data_out_2_OUTMUX
    );
  data_out_2_OMUX : X_BUF
    port map (
      I => Q_n0011(2),
      O => data_out_2_OD
    );
  data_out_3_OBUFT : X_TRI
    port map (
      I => data_out_3_OUTMUX,
      CTL => data_out_3_ENABLE,
      O => data_out(3)
    );
  data_out_3_ENABLEINV : X_INV
    port map (
      I => data_out_3_TORGTS,
      O => data_out_3_ENABLE
    );
  data_out_3_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => Mtrien_data_out_4,
      O => data_out_3_TORGTS
    );
  data_out_3_OUTMUX_24 : X_BUF
    port map (
      I => Mtridata_data_out(3),
      O => data_out_3_OUTMUX
    );
  data_out_3_OMUX : X_BUF
    port map (
      I => Q_n0011(3),
      O => data_out_3_OD
    );
  data_out_4_OBUFT : X_TRI
    port map (
      I => data_out_4_OUTMUX,
      CTL => data_out_4_ENABLE,
      O => data_out(4)
    );
  data_out_4_ENABLEINV : X_INV
    port map (
      I => data_out_4_TORGTS,
      O => data_out_4_ENABLE
    );
  data_out_4_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => Mtrien_data_out_3,
      O => data_out_4_TORGTS
    );
  data_out_4_OUTMUX_25 : X_BUF
    port map (
      I => Mtridata_data_out(4),
      O => data_out_4_OUTMUX
    );
  data_out_4_OMUX : X_BUF
    port map (
      I => Q_n0011(4),
      O => data_out_4_OD
    );
  data_in_0_IMUX : X_BUF
    port map (
      I => data_in_0_IBUF_5,
      O => data_in_0_IBUF
    );
  data_in_0_IBUF_26 : X_BUF
    port map (
      I => data_in(0),
      O => data_in_0_IBUF_5
    );
  data_out_5_OBUFT : X_TRI
    port map (
      I => data_out_5_OUTMUX,
      CTL => data_out_5_ENABLE,
      O => data_out(5)
    );
  data_out_5_ENABLEINV : X_INV
    port map (
      I => data_out_5_TORGTS,
      O => data_out_5_ENABLE
    );
  data_out_5_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => Mtrien_data_out_2,
      O => data_out_5_TORGTS
    );
  data_out_5_OUTMUX_27 : X_BUF
    port map (
      I => Mtridata_data_out(5),
      O => data_out_5_OUTMUX
    );
  data_out_5_OMUX : X_BUF
    port map (
      I => Q_n0011(5),
      O => data_out_5_OD
    );
  Mtrien_data_out_28 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0012,
      CE => Q_n0038,
      CLK => clock_BUFGP,
      SET => GND,
      RST => data_out_0_TFF_RST,
      O => Mtrien_data_out
    );
  data_out_0_TFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => data_out_0_TFF_RST
    );
  data_in_1_IMUX : X_BUF
    port map (
      I => data_in_1_IBUF_6,
      O => data_in_1_IBUF
    );
  data_in_1_IBUF_29 : X_BUF
    port map (
      I => data_in(1),
      O => data_in_1_IBUF_6
    );
  data_out_6_OBUFT : X_TRI
    port map (
      I => data_out_6_OUTMUX,
      CTL => data_out_6_ENABLE,
      O => data_out(6)
    );
  data_out_6_ENABLEINV : X_INV
    port map (
      I => data_out_6_TORGTS,
      O => data_out_6_ENABLE
    );
  data_out_6_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => Mtrien_data_out_1,
      O => data_out_6_TORGTS
    );
  data_out_6_OUTMUX_30 : X_BUF
    port map (
      I => Mtridata_data_out(6),
      O => data_out_6_OUTMUX
    );
  data_out_6_OMUX : X_BUF
    port map (
      I => Q_n0011(6),
      O => data_out_6_OD
    );
  data_in_2_IMUX : X_BUF
    port map (
      I => data_in_2_IBUF_7,
      O => data_in_2_IBUF
    );
  data_in_2_IBUF_31 : X_BUF
    port map (
      I => data_in(2),
      O => data_in_2_IBUF_7
    );
  data_out_7_OBUFT : X_TRI
    port map (
      I => data_out_7_OUTMUX,
      CTL => data_out_7_ENABLE,
      O => data_out(7)
    );
  data_out_7_ENABLEINV : X_INV
    port map (
      I => data_out_7_TORGTS,
      O => data_out_7_ENABLE
    );
  data_out_7_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => Mtrien_data_out_0,
      O => data_out_7_TORGTS
    );
  data_out_7_OUTMUX_32 : X_BUF
    port map (
      I => Mtridata_data_out(7),
      O => data_out_7_OUTMUX
    );
  data_out_7_OMUX : X_BUF
    port map (
      I => Q_n0011(7),
      O => data_out_7_OD
    );
  data_in_3_IMUX : X_BUF
    port map (
      I => data_in_3_IBUF_8,
      O => data_in_3_IBUF
    );
  data_in_3_IBUF_33 : X_BUF
    port map (
      I => data_in(3),
      O => data_in_3_IBUF_8
    );
  data_in_4_IMUX : X_BUF
    port map (
      I => data_in_4_IBUF_9,
      O => data_in_4_IBUF
    );
  data_in_4_IBUF_34 : X_BUF
    port map (
      I => data_in(4),
      O => data_in_4_IBUF_9
    );
  data_in_5_IMUX : X_BUF
    port map (
      I => data_in_5_IBUF_10,
      O => data_in_5_IBUF
    );
  data_in_5_IBUF_35 : X_BUF
    port map (
      I => data_in(5),
      O => data_in_5_IBUF_10
    );
  data_in_6_IMUX : X_BUF
    port map (
      I => data_in_6_IBUF_11,
      O => data_in_6_IBUF
    );
  data_in_6_IBUF_36 : X_BUF
    port map (
      I => data_in(6),
      O => data_in_6_IBUF_11
    );
  waddr_0_IMUX : X_BUF
    port map (
      I => waddr_0_IBUF_12,
      O => waddr_0_IBUF
    );
  waddr_0_IBUF_37 : X_BUF
    port map (
      I => waddr(0),
      O => waddr_0_IBUF_12
    );
  data_in_7_IMUX : X_BUF
    port map (
      I => data_in_7_IBUF_13,
      O => data_in_7_IBUF
    );
  data_in_7_IBUF_38 : X_BUF
    port map (
      I => data_in(7),
      O => data_in_7_IBUF_13
    );
  waddr_1_IMUX : X_BUF
    port map (
      I => waddr_1_IBUF_14,
      O => waddr_1_IBUF
    );
  waddr_1_IBUF_39 : X_BUF
    port map (
      I => waddr(1),
      O => waddr_1_IBUF_14
    );
  waddr_2_IMUX : X_BUF
    port map (
      I => waddr_2_IBUF_15,
      O => waddr_2_IBUF
    );
  waddr_2_IBUF_40 : X_BUF
    port map (
      I => waddr(2),
      O => waddr_2_IBUF_15
    );
  Mmux_n0011_inst_mux_f5_0 : X_MUX2
    port map (
      IA => Mmux_n0011_inst_lut3_01_O,
      IB => Mmux_n0011_inst_lut3_110_O,
      SEL => raddr_1_IBUF,
      O => Mmux_n0011_net2_F5MUX
    );
  Mmux_n0011_inst_lut3_110 : X_LUT4
    generic map(
      INIT => X"ACAC"
    )
    port map (
      ADR0 => data_3_0,
      ADR1 => data_2_0,
      ADR2 => raddr_0_IBUF,
      ADR3 => VCC,
      O => Mmux_n0011_inst_lut3_110_O
    );
  Mmux_n0011_inst_lut3_01 : X_LUT4
    generic map(
      INIT => X"FA0A"
    )
    port map (
      ADR0 => data_0_0,
      ADR1 => VCC,
      ADR2 => raddr_0_IBUF,
      ADR3 => data_1_0,
      O => Mmux_n0011_inst_lut3_01_O
    );
  Mmux_n0011_net2_F5USED : X_BUF
    port map (
      I => Mmux_n0011_net2_F5MUX,
      O => Mmux_n0011_net2
    );
  Mmux_n0011_inst_mux_f5_1 : X_MUX2
    port map (
      IA => Mmux_n0011_inst_lut3_210_O,
      IB => Mmux_n0011_inst_lut3_32_O,
      SEL => raddr_1_IBUF,
      O => Mmux_n0011_net5
    );
  Mmux_n0011_inst_lut3_32 : X_LUT4
    generic map(
      INIT => X"F3C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => raddr_0_IBUF,
      ADR2 => data_7_0,
      ADR3 => data_6_0,
      O => Mmux_n0011_inst_lut3_32_O
    );
  Mmux_n0011_inst_lut3_210 : X_LUT4
    generic map(
      INIT => X"FC30"
    )
    port map (
      ADR0 => VCC,
      ADR1 => raddr_0_IBUF,
      ADR2 => data_4_0,
      ADR3 => data_5_0,
      O => Mmux_n0011_inst_lut3_210_O
    );
  Q_n0011_0_YUSED : X_BUF
    port map (
      I => Q_n0011_0_F6MUX,
      O => Q_n0011(0)
    );
  Mmux_n0011_inst_mux_f6_0 : X_MUX2
    port map (
      IA => Mmux_n0011_net2,
      IB => Mmux_n0011_net5,
      SEL => raddr_2_IBUF,
      O => Q_n0011_0_F6MUX
    );
  Mmux_n0011_inst_mux_f5_2 : X_MUX2
    port map (
      IA => Mmux_n0011_inst_lut3_41_O,
      IB => Mmux_n0011_inst_lut3_51_O,
      SEL => raddr_1_IBUF,
      O => Mmux_n0011_net9_F5MUX
    );
  Mmux_n0011_inst_lut3_51 : X_LUT4
    generic map(
      INIT => X"CCAA"
    )
    port map (
      ADR0 => data_2_1,
      ADR1 => data_3_1,
      ADR2 => VCC,
      ADR3 => raddr_0_IBUF,
      O => Mmux_n0011_inst_lut3_51_O
    );
  Mmux_n0011_inst_lut3_41 : X_LUT4
    generic map(
      INIT => X"EE44"
    )
    port map (
      ADR0 => raddr_0_IBUF,
      ADR1 => data_0_1,
      ADR2 => VCC,
      ADR3 => data_1_1,
      O => Mmux_n0011_inst_lut3_41_O
    );
  Mmux_n0011_net9_F5USED : X_BUF
    port map (
      I => Mmux_n0011_net9_F5MUX,
      O => Mmux_n0011_net9
    );
  Mmux_n0011_inst_mux_f5_3 : X_MUX2
    port map (
      IA => Mmux_n0011_inst_lut3_61_O,
      IB => Mmux_n0011_inst_lut3_71_O,
      SEL => raddr_1_IBUF,
      O => Mmux_n0011_net12
    );
  Mmux_n0011_inst_lut3_71 : X_LUT4
    generic map(
      INIT => X"E2E2"
    )
    port map (
      ADR0 => data_6_1,
      ADR1 => raddr_0_IBUF,
      ADR2 => data_7_1,
      ADR3 => VCC,
      O => Mmux_n0011_inst_lut3_71_O
    );
  Mmux_n0011_inst_lut3_61 : X_LUT4
    generic map(
      INIT => X"EE44"
    )
    port map (
      ADR0 => raddr_0_IBUF,
      ADR1 => data_4_1,
      ADR2 => VCC,
      ADR3 => data_5_1,
      O => Mmux_n0011_inst_lut3_61_O
    );
  Q_n0011_1_YUSED : X_BUF
    port map (
      I => Q_n0011_1_F6MUX,
      O => Q_n0011(1)
    );
  Mmux_n0011_inst_mux_f6_1 : X_MUX2
    port map (
      IA => Mmux_n0011_net9,
      IB => Mmux_n0011_net12,
      SEL => raddr_2_IBUF,
      O => Q_n0011_1_F6MUX
    );
  Mmux_n0011_inst_mux_f5_4 : X_MUX2
    port map (
      IA => Mmux_n0011_inst_lut3_81_O,
      IB => Mmux_n0011_inst_lut3_91_O,
      SEL => raddr_1_IBUF,
      O => Mmux_n0011_net16_F5MUX
    );
  Mmux_n0011_inst_lut3_91 : X_LUT4
    generic map(
      INIT => X"BB88"
    )
    port map (
      ADR0 => data_3_2,
      ADR1 => raddr_0_IBUF,
      ADR2 => VCC,
      ADR3 => data_2_2,
      O => Mmux_n0011_inst_lut3_91_O
    );
  Mmux_n0011_inst_lut3_81 : X_LUT4
    generic map(
      INIT => X"AACC"
    )
    port map (
      ADR0 => data_1_2,
      ADR1 => data_0_2,
      ADR2 => VCC,
      ADR3 => raddr_0_IBUF,
      O => Mmux_n0011_inst_lut3_81_O
    );
  Mmux_n0011_net16_F5USED : X_BUF
    port map (
      I => Mmux_n0011_net16_F5MUX,
      O => Mmux_n0011_net16
    );
  Mmux_n0011_inst_mux_f5_5 : X_MUX2
    port map (
      IA => Mmux_n0011_inst_lut3_101_O,
      IB => Mmux_n0011_inst_lut3_111_O,
      SEL => raddr_1_IBUF,
      O => Mmux_n0011_net19
    );
  Mmux_n0011_inst_lut3_111 : X_LUT4
    generic map(
      INIT => X"DD88"
    )
    port map (
      ADR0 => raddr_0_IBUF,
      ADR1 => data_7_2,
      ADR2 => VCC,
      ADR3 => data_6_2,
      O => Mmux_n0011_inst_lut3_111_O
    );
  Mmux_n0011_inst_lut3_101 : X_LUT4
    generic map(
      INIT => X"DD88"
    )
    port map (
      ADR0 => raddr_0_IBUF,
      ADR1 => data_5_2,
      ADR2 => VCC,
      ADR3 => data_4_2,
      O => Mmux_n0011_inst_lut3_101_O
    );
  Q_n0011_2_YUSED : X_BUF
    port map (
      I => Q_n0011_2_F6MUX,
      O => Q_n0011(2)
    );
  Mmux_n0011_inst_mux_f6_2 : X_MUX2
    port map (
      IA => Mmux_n0011_net16,
      IB => Mmux_n0011_net19,
      SEL => raddr_2_IBUF,
      O => Q_n0011_2_F6MUX
    );
  Mmux_n0011_inst_mux_f5_6 : X_MUX2
    port map (
      IA => Mmux_n0011_inst_lut3_121_O,
      IB => Mmux_n0011_inst_lut3_131_O,
      SEL => raddr_1_IBUF,
      O => Mmux_n0011_net23_F5MUX
    );
  Mmux_n0011_inst_lut3_131 : X_LUT4
    generic map(
      INIT => X"CCF0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => data_3_3,
      ADR2 => data_2_3,
      ADR3 => raddr_0_IBUF,
      O => Mmux_n0011_inst_lut3_131_O
    );
  Mmux_n0011_inst_lut3_121 : X_LUT4
    generic map(
      INIT => X"CCAA"
    )
    port map (
      ADR0 => data_0_3,
      ADR1 => data_1_3,
      ADR2 => VCC,
      ADR3 => raddr_0_IBUF,
      O => Mmux_n0011_inst_lut3_121_O
    );
  Mmux_n0011_net23_F5USED : X_BUF
    port map (
      I => Mmux_n0011_net23_F5MUX,
      O => Mmux_n0011_net23
    );
  Mmux_n0011_inst_mux_f5_7 : X_MUX2
    port map (
      IA => Mmux_n0011_inst_lut3_141_O,
      IB => Mmux_n0011_inst_lut3_151_O,
      SEL => raddr_1_IBUF,
      O => Mmux_n0011_net26