my_sram.syr

FPGA系统的sram的软仿真设计

Release 6.3i - xst G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
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--> Parameter xsthdpdir set to ./xst
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--> Reading design: my_sram.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : my_sram.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : my_sram
Output Format                      : NGC
Target Device                      : xc2s15-6-cs144

---- Source Options
Top Module Name                    : my_sram
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : my_sram.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO
tristate2logic                     : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file G:/MyFPGA/my_sram.vhd in Library work.
Architecture behavioral of Entity my_sram is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <my_sram> (Architecture <behavioral>).
Entity <my_sram> analyzed. Unit <my_sram> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <my_sram>.
    Related source file is G:/MyFPGA/my_sram.vhd.
    Found 8-bit tristate buffer for signal <data_out>.
    Found 8-bit 8-to-1 multiplexer for signal <$n0002> created at line 37.
    Found 64-bit register for signal <mem>.
    Found 8-bit register for signal <Mtridata_data_out> created at line 37.
    Found 1-bit register for signal <Mtrien_data_out> created at line 37.
    Summary:
	inferred  73 D-type flip-flop(s).
	inferred   8 Multiplexer(s).
	inferred   8 Tristate(s).
Unit <my_sram> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 10
 1-bit register                    : 1
 8-bit register                    : 9
# Multiplexers                     : 1
 8-bit 8-to-1 multiplexer          : 1
# Tristates                        : 1
 8-bit tristate buffer             : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <my_sram> ...
Loading device for application Xst from file '2s15.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block my_sram, actual ratio is 28.
FlipFlop Mtrien_data_out has been replicated 7 time(s) to handle iob=true attribute.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : my_sram.ngr
Top Level Output File Name         : my_sram
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 26

Macro Statistics :
# Registers                        : 10
#      1-bit register              : 1
#      8-bit register              : 9
# Multiplexers                     : 1
#      8-bit 8-to-1 multiplexer    : 1
# Tristates                        : 1
#      8-bit tristate buffer       : 1

Cell Usage :
# BELS                             : 68
#      LUT1                        : 2
#      LUT3                        : 10
#      LUT3_L                      : 32
#      MUXF5                       : 16
#      MUXF6                       : 8
# FlipFlops/Latches                : 80
#      FD                          : 8
#      FDE                         : 64
#      FDP                         : 8
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 25
#      IBUF                        : 17
#      OBUFT                       : 8
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s15cs144-6 

 Number of Slices:                      57  out of    192    29%  
 Number of Slice Flip Flops:            80  out of    384    20%  
 Number of 4 input LUTs:                44  out of    384    11%  
 Number of bonded IOBs:                 25  out of     90    27%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 80    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 4.009ns (Maximum Frequency: 249.439MHz)
   Minimum input arrival time before clock: 7.377ns
   Maximum output required time after clock: 6.927ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk'
Delay:               4.009ns (Levels of Logic = 3)
  Source:            mem_0_6 (FF)
  Destination:       Mtridata_data_out_6 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: mem_0_6 to Mtridata_data_out_6
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              1   1.085   1.035  mem_0_6 (mem_0_6)
     LUT3_L:I1->LO         1   0.549   0.000  Mmux__n0002_inst_lut3_241 (Mmux__n0002__net42)
     MUXF5:I0->O           1   0.315   0.000  Mmux__n0002_inst_mux_f5_12 (Mmux__n0002__net44)
     MUXF6:I0->O           1   0.316   0.000  Mmux__n0002_inst_mux_f6_6 (_n0002<6>)
     FD:D                      0.709          Mtridata_data_out_6
    ----------------------------------------
    Total                      4.009ns (2.974ns logic, 1.035ns route)
                                       (74.2% logic, 25.8% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Offset:              7.377ns (Levels of Logic = 3)
  Source:            cs (PAD)
  Destination:       mem_0_6 (FF)
  Destination Clock: clk rising

  Data Path: cs to mem_0_6
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             3   0.776   1.332  cs_IBUF (cs_IBUF)
     LUT3:I1->O            4   0.549   1.440  Ker10351 (N1037)
     LUT3:I0->O            8   0.549   1.845  _n00101 (_n0010)
     FDE:CE                    0.886          mem_7_0
    ----------------------------------------
    Total                      7.377ns (2.760ns logic, 4.617ns route)
                                       (37.4% logic, 62.6% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Offset:              6.927ns (Levels of Logic = 1)
  Source:            Mtrien_data_out_1 (FF)
  Destination:       data_out<7> (PAD)
  Source Clock:      clk rising

  Data Path: Mtrien_data_out_1 to data_out<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDP:C->Q              1   1.085   1.035  Mtrien_data_out_1 (Mtrien_data_out_0)
     OBUFT:T->O                4.807          data_out_7_OBUFT (data_out<7>)
    ----------------------------------------
    Total                      6.927ns (5.892ns logic, 1.035ns route)
                                       (85.1% logic, 14.9% route)

=========================================================================
CPU : 2.42 / 3.47 s | Elapsed : 2.00 / 3.00 s
 
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Total memory usage is 55820 kilobytes