my_sram_test_vhd_tb.tdo

FPGA系统的sram的软仿真设计

## NOTE: Do not edit this file.
## Auto generated by Project Navigator for VHDL Post-PAR Simulation
##
vlib work
## Compile Post-PAR Model for Module my_sram
vcom -87 -explicit  my_sram_timesim.vhd
vcom -93 -explicit  Test.vhd
vsim -t 1ps -sdfmax /UUT=my_sram_timesim.sdf  -lib work my_sram_test_vhd_tb
do my_sram_test_vhd_tb.udo
view wave
add wave *
view structure
view signals
run 1000ns
## End