myfpga.gfl

FPGA系统的sram的软仿真设计

# XST (Creating Lso File) : 
my_sram.lso
# Check Syntax
my_sram.stx
my_sram.ngc
# xst flow : RunXST
my_sram.syr
my_sram.prj
my_sram.sprj
my_sram.ana
my_sram.stx
my_sram.cmd_log
my_sram.ngc
my_sram.ngr
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
TestWave.vhw
TestWave.ano
TestWave.tfw
# ModelSim : Simulate Behavioral VHDL Model
TestWave.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# View RTL Schematic
my_sram.ngr
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
my_sram.lso
# Check Syntax
my_sram.stx
my_sram.ngc
# XST (Creating Lso File) : 
my_sram.lso
# xst flow : RunXST
my_sram.syr
my_sram.prj
my_sram.sprj
my_sram.ana
my_sram.stx
my_sram.cmd_log
my_sram.ngc
my_sram.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
g:\myfpga/_ngo
my_sram.ngd
my_sram_ngdbuild.nav
my_sram.bld
my_sram.ucf.untf
my_sram.cmd_log
# ModelSim : Simulate Behavioral VHDL Model
TestWave.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# XST (Creating Lso File) : 
my_sram.lso
# xst flow : RunXST
my_sram.syr
my_sram.prj
my_sram.sprj
my_sram.ana
my_sram.stx
my_sram.cmd_log
my_sram.ngc
my_sram.ngr
# XST (Creating Lso File) : 
my_sram.lso
# xst flow : RunXST
my_sram.syr
my_sram.prj
my_sram.sprj
my_sram.ana
my_sram.stx
my_sram.cmd_log
my_sram.ngc
my_sram.ngr
# XST (Creating Lso File) : 
my_sram.lso
# xst flow : RunXST
my_sram.syr
my_sram.prj
my_sram.sprj
my_sram.ana
my_sram.stx
my_sram.cmd_log
my_sram.ngc
my_sram.ngr
# ProjNav -> New -> Test Bench
__projnav/createTB.err
# XST (Creating Lso File) : 
my_sram.lso
# xst flow : RunXST
my_sram.syr
my_sram.prj
my_sram.sprj
my_sram.ana
my_sram.stx
my_sram.cmd_log
my_sram.ngc
my_sram.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
g:\myfpga/_ngo
my_sram.ngd
my_sram_ngdbuild.nav
my_sram.bld
my_sram.ucf.untf
my_sram.cmd_log
# Implementation : Map
my_sram_map.ncd
my_sram.ngm
my_sram.pcf
my_sram.nc1
my_sram.mrp
my_sram_map.mrp
my_sram.mdf
__projnav/map.log
my_sram.cmd_log
MAP_NO_GUIDE_FILE_CPF "my_sram"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
my_sram.twr
my_sram.twx
my_sram.tsi
my_sram.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
my_sram.ncd
my_sram.par
my_sram.pad
my_sram_pad.txt
my_sram_pad.csv
my_sram.pad_txt
my_sram.dly
reportgen.log
my_sram.xpi
my_sram.grf
my_sram.itr
my_sram_last_par.ncd
__projnav/par.log
my_sram.placed_ncd_tracker
my_sram.routed_ncd_tracker
my_sram.cmd_log
PAR_NO_GUIDE_FILE_CPF "my_sram"
# Implementation : Generate Post-Par Simulation Model
my_sram_timesim.vhd
my_sram_timesim.sdf
my_sram_timesim.sdf
my_sram_timesim.vhd
my_sram_timesim.nlf
my_sram.par_nlf
my_sram.vhdsim_par
my_sram.cmd_log
__projnav/netgen_par_tcl.rsp
# ModelSim : Simulate Post-Place & Route VHDL Model
my_sram_test_vhd_tb.tdo
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# ProjNav -> New -> Test Bench
__projnav/createTB.err
# ModelSim : Simulate Post-Place & Route VHDL Model
my_sram_test_vhd_tb.tdo
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# Implementation : Generate Post-Par Simulation Model
my_sram_timesim.vhd
my_sram_timesim.sdf
my_sram_timesim.sdf
my_sram_timesim.vhd
my_sram_timesim.nlf
my_sram.par_nlf
my_sram.vhdsim_par
my_sram.cmd_log
__projnav/netgen_par_tcl.rsp
# ModelSim : Simulate Behavioral VHDL Model
my_sram_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
my_sram_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
my_sram_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
my_sram_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
my_sram_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
my_sram_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# XST (Creating Lso File) : 
my_sram.lso
# xst flow : RunXST
my_sram.syr
my_sram.prj
my_sram.sprj
my_sram.ana
my_sram.stx
my_sram.cmd_log
my_sram.ngc
my_sram.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
g:\myfpga/_ngo
my_sram.ngd
my_sram_ngdbuild.nav
my_sram.bld
my_sram.ucf.untf
my_sram.cmd_log
# Implementation : Map
my_sram_map.ncd
my_sram.ngm
my_sram.pcf
my_sram.nc1
my_sram.mrp
my_sram_map.mrp
my_sram.mdf
__projnav/map.log
my_sram.cmd_log
MAP_NO_GUIDE_FILE_CPF "my_sram"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
my_sram.twr
my_sram.twx
my_sram.tsi
my_sram.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
my_sram.ncd
my_sram.par
my_sram.pad
my_sram_pad.txt
my_sram_pad.csv
my_sram.pad_txt
my_sram.dly
reportgen.log
my_sram.xpi
my_sram.grf
my_sram.itr
my_sram_last_par.ncd
__projnav/par.log
my_sram.placed_ncd_tracker
my_sram.routed_ncd_tracker
my_sram.cmd_log
PAR_NO_GUIDE_FILE_CPF "my_sram"
# Implementation : Generate Post-Par Simulation Model
my_sram_timesim.vhd
my_sram_timesim.sdf
my_sram_timesim.sdf
my_sram_timesim.vhd
my_sram_timesim.nlf
my_sram.par_nlf
my_sram.vhdsim_par
my_sram.cmd_log
__projnav/netgen_par_tcl.rsp
# ModelSim : Simulate Post-Place & Route VHDL Model
my_sram_test_vhd_tb.tdo
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# XST (Creating Lso File) : 
my_sram.lso
# xst flow : RunXST
my_sram.syr
my_sram.prj
my_sram.sprj
my_sram.ana
my_sram.stx
my_sram.cmd_log
my_sram.ngc
my_sram.ngr
# View RTL Schematic
my_sram.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
g:\myfpga/_ngo
my_sram.ngd
my_sram_ngdbuild.nav
my_sram.bld
my_sram.ucf.untf
my_sram.cmd_log
# Implementation : Map
my_sram_map.ncd
my_sram.ngm
my_sram.pcf
my_sram.nc1
my_sram.mrp
my_sram_map.mrp
my_sram.mdf
__projnav/map.log
my_sram.cmd_log
MAP_NO_GUIDE_FILE_CPF "my_sram"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
my_sram.twr
my_sram.twx
my_sram.tsi
my_sram.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
my_sram.ncd
my_sram.par
my_sram.pad
my_sram_pad.txt
my_sram_pad.csv
my_sram.pad_txt
my_sram.dly
reportgen.log
my_sram.xpi
my_sram.grf
my_sram.itr
my_sram_last_par.ncd
__projnav/par.log
my_sram.placed_ncd_tracker
my_sram.routed_ncd_tracker
my_sram.cmd_log
PAR_NO_GUIDE_FILE_CPF "my_sram"
# Implementation : Generate Post-Par Simulation Model
my_sram_timesim.vhd
my_sram_timesim.sdf
my_sram_timesim.sdf
my_sram_timesim.vhd
my_sram_timesim.nlf
my_sram.par_nlf
my_sram.vhdsim_par
my_sram.cmd_log
__projnav/netgen_par_tcl.rsp
# ModelSim : Simulate Post-Place & Route VHDL Model
my_sram_test_vhd_tb.tdo
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# XST (Creating Lso File) : 
my_sram.lso
# xst flow : RunXST
my_sram.syr
my_sram.prj
my_sram.sprj
my_sram.ana
my_sram.stx
my_sram.cmd_log
my_sram.ngc
my_sram.ngr
# XST (Creating Lso File) : 
my_sram.lso
# xst flow : RunXST
my_sram.syr
my_sram.prj
my_sram.sprj
my_sram.ana
my_sram.stx
my_sram.cmd_log
my_sram.ngc
my_sram.ngr
# XST (Creating Lso File) : 
my_sram.lso
# xst flow : RunXST
my_sram.syr
my_sram.prj
my_sram.sprj
my_sram.ana
my_sram.stx
my_sram.cmd_log
my_sram.ngc
my_sram.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
g:\myfpga/_ngo
my_sram.ngd
my_sram_ngdbuild.nav
my_sram.bld
my_sram.ucf.untf
my_sram.cmd_log
# Implementation : Map
my_sram_map.ncd
my_sram.ngm
my_sram.pcf
my_sram.nc1
my_sram.mrp
my_sram_map.mrp
my_sram.mdf
__projnav/map.log
my_sram.cmd_log
MAP_NO_GUIDE_FILE_CPF "my_sram"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
my_sram.twr
my_sram.twx
my_sram.tsi
my_sram.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
my_sram.ncd
my_sram.par
my_sram.pad
my_sram_pad.txt
my_sram_pad.csv
my_sram.pad_txt
my_sram.dly
reportgen.log
my_sram.xpi
my_sram.grf
my_sram.itr
my_sram_last_par.ncd
__projnav/par.log
my_sram.placed_ncd_tracker
my_sram.routed_ncd_tracker
my_sram.cmd_log
PAR_NO_GUIDE_FILE_CPF "my_sram"
# Implementation : Generate Post-Par Simulation Model
my_sram_timesim.vhd
my_sram_timesim.sdf
my_sram_timesim.sdf
my_sram_timesim.vhd
my_sram_timesim.nlf
my_sram.par_nlf
my_sram.vhdsim_par
my_sram.cmd_log
__projnav/netgen_par_tcl.rsp
# View RTL Schematic
my_sram.ngr
# XST (Creating Lso File) : 
my_sram.lso
# xst flow : RunXST
my_sram.syr
my_sram.prj
my_sram.sprj
my_sram.ana
my_sram.stx
my_sram.cmd_log
my_sram.ngc
my_sram.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
g:\myfpga/_ngo
my_sram.ngd
my_sram_ngdbuild.nav
my_sram.bld
my_sram.ucf.untf
my_sram.cmd_log
# Implementation : Map
my_sram_map.ncd
my_sram.ngm
my_sram.pcf
my_sram.nc1
my_sram.mrp
my_sram_map.mrp
my_sram.mdf
__projnav/map.log
my_sram.cmd_log
MAP_NO_GUIDE_FILE_CPF "my_sram"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
my_sram.twr
my_sram.twx
my_sram.tsi
my_sram.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
my_sram.ncd
my_sram.par
my_sram.pad
my_sram_pad.txt
my_sram_pad.csv
my_sram.pad_txt
my_sram.dly
reportgen.log
my_sram.xpi
my_sram.grf
my_sram.itr
my_sram_last_par.ncd
__projnav/par.log
my_sram.placed_ncd_tracker
my_sram.routed_ncd_tracker
my_sram.cmd_log
PAR_NO_GUIDE_FILE_CPF "my_sram"
# Implementation : Generate Post-Par Simulation Model
my_sram_timesim.vhd
my_sram_timesim.sdf
my_sram_timesim.sdf
my_sram_timesim.vhd
my_sram_timesim.nlf
my_sram.par_nlf
my_sram.vhdsim_par
my_sram.cmd_log
__projnav/netgen_par_tcl.rsp
# ModelSim : Simulate Behavioral VHDL Model
my_sram_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# XST (Creating Lso File) : 
my_sram.lso
# xst flow : RunXST
my_sram.syr
my_sram.prj
my_sram.sprj
my_sram.ana
my_sram.stx
my_sram.cmd_log
my_sram.ngc
my_sram.ngr
# XST (Creating Lso File) : 
my_sram.lso
# xst flow : RunXST
my_sram.syr
my_sram.prj
my_sram.sprj
my_sram.ana
my_sram.stx
my_sram.cmd_log
my_sram.ngc
my_sram.ngr
# XST (Creating Lso File) : 
my_sram.lso
# xst flow : RunXST
my_sram.syr
my_sram.prj
my_sram.sprj
my_sram.ana
my_sram.stx
my_sram.cmd_log
my_sram.ngc
my_sram.ngr
# Check Syntax
my_sram.stx
my_sram.ngc
# XST (Creating Lso File) : 
my_sram.lso
# xst flow : RunXST
my_sram.syr
my_sram.prj
my_sram.sprj
my_sram.ana
my_sram.stx
my_sram.cmd_log
my_sram.ngc
my_sram.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
g:\myfpga/_ngo
my_sram.ngd
my_sram_ngdbuild.nav
my_sram.bld
my_sram.ucf.untf
my_sram.cmd_log
# Implementation : Map
my_sram_map.ncd
my_sram.ngm
my_sram.pcf
my_sram.nc1
my_sram.mrp
my_sram_map.mrp
my_sram.mdf
__projnav/map.log
my_sram.cmd_log
MAP_NO_GUIDE_FILE_CPF "my_sram"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
my_sram.twr
my_sram.twx
my_sram.tsi
my_sram.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
my_sram.ncd
my_sram.par
my_sram.pad
my_sram_pad.txt
my_sram_pad.csv
my_sram.pad_txt
my_sram.dly
reportgen.log
my_sram.xpi
my_sram.grf
my_sram.itr
my_sram_last_par.ncd
__projnav/par.log