my_sram_translate.vhd

FPGA系统的sram的软仿真设计

    );
  Mmux_n0004_Result_3_1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => Q_n0048,
      ADR1 => data_in_3_IBUF,
      ADR2 => data_2_3,
      O => Mmux_n0004_Result_3_1_O
    );
  Mmux_n0004_Result_2_1_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0004_Result_2_1_O,
      O => Q_n0004(2)
    );
  Mmux_n0004_Result_2_1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => Q_n0048,
      ADR1 => data_in_2_IBUF,
      ADR2 => data_2_2,
      O => Mmux_n0004_Result_2_1_O
    );
  Mmux_n0004_Result_1_1_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0004_Result_1_1_O,
      O => Q_n0004(1)
    );
  Mmux_n0004_Result_1_1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => Q_n0048,
      ADR1 => data_in_1_IBUF,
      ADR2 => data_2_1,
      O => Mmux_n0004_Result_1_1_O
    );
  Mmux_n0004_Result_0_1_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0004_Result_0_1_O,
      O => Q_n0004(0)
    );
  Mmux_n0004_Result_0_1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => Q_n0048,
      ADR1 => data_in_0_IBUF,
      ADR2 => data_2_0,
      O => Mmux_n0004_Result_0_1_O
    );
  Mmux_n0005_Result_6_1_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0005_Result_6_1_O,
      O => Q_n0005(6)
    );
  Mmux_n0005_Result_6_1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => Q_n0050,
      ADR1 => data_in_6_IBUF,
      ADR2 => data_3_6,
      O => Mmux_n0005_Result_6_1_O
    );
  Mmux_n0005_Result_5_1_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0005_Result_5_1_O,
      O => Q_n0005(5)
    );
  Mmux_n0005_Result_5_1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => Q_n0050,
      ADR1 => data_in_5_IBUF,
      ADR2 => data_3_5,
      O => Mmux_n0005_Result_5_1_O
    );
  Mmux_n0005_Result_4_1_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0005_Result_4_1_O,
      O => Q_n0005(4)
    );
  Mmux_n0005_Result_4_1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => Q_n0050,
      ADR1 => data_in_4_IBUF,
      ADR2 => data_3_4,
      O => Mmux_n0005_Result_4_1_O
    );
  Mmux_n0005_Result_3_1_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0005_Result_3_1_O,
      O => Q_n0005(3)
    );
  Mmux_n0005_Result_3_1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => Q_n0050,
      ADR1 => data_in_3_IBUF,
      ADR2 => data_3_3,
      O => Mmux_n0005_Result_3_1_O
    );
  Mmux_n0005_Result_2_1_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0005_Result_2_1_O,
      O => Q_n0005(2)
    );
  Mmux_n0005_Result_2_1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => Q_n0050,
      ADR1 => data_in_2_IBUF,
      ADR2 => data_3_2,
      O => Mmux_n0005_Result_2_1_O
    );
  Mmux_n0005_Result_1_1_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0005_Result_1_1_O,
      O => Q_n0005(1)
    );
  Mmux_n0005_Result_1_1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => Q_n0050,
      ADR1 => data_in_1_IBUF,
      ADR2 => data_3_1,
      O => Mmux_n0005_Result_1_1_O
    );
  Mmux_n0005_Result_0_1_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0005_Result_0_1_O,
      O => Q_n0005(0)
    );
  Mmux_n0005_Result_0_1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => Q_n0050,
      ADR1 => data_in_0_IBUF,
      ADR2 => data_3_0,
      O => Mmux_n0005_Result_0_1_O
    );
  Mmux_n0006_Result_6_1_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0006_Result_6_1_O,
      O => Q_n0006(6)
    );
  Mmux_n0006_Result_6_1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => Q_n0052,
      ADR1 => data_in_6_IBUF,
      ADR2 => data_4_6,
      O => Mmux_n0006_Result_6_1_O
    );
  Mmux_n0006_Result_5_1_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0006_Result_5_1_O,
      O => Q_n0006(5)
    );
  Mmux_n0006_Result_5_1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => Q_n0052,
      ADR1 => data_in_5_IBUF,
      ADR2 => data_4_5,
      O => Mmux_n0006_Result_5_1_O
    );
  Mmux_n0006_Result_4_1_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0006_Result_4_1_O,
      O => Q_n0006(4)
    );
  Mmux_n0006_Result_4_1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => Q_n0052,
      ADR1 => data_in_4_IBUF,
      ADR2 => data_4_4,
      O => Mmux_n0006_Result_4_1_O
    );
  Mmux_n0006_Result_3_1_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0006_Result_3_1_O,
      O => Q_n0006(3)
    );
  Mmux_n0006_Result_3_1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => Q_n0052,
      ADR1 => data_in_3_IBUF,
      ADR2 => data_4_3,
      O => Mmux_n0006_Result_3_1_O
    );
  Mmux_n0006_Result_2_1_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0006_Result_2_1_O,
      O => Q_n0006(2)
    );
  Mmux_n0006_Result_2_1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => Q_n0052,
      ADR1 => data_in_2_IBUF,
      ADR2 => data_4_2,
      O => Mmux_n0006_Result_2_1_O
    );
  Mmux_n0006_Result_1_1_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0006_Result_1_1_O,
      O => Q_n0006(1)
    );
  Mmux_n0006_Result_1_1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => Q_n0052,
      ADR1 => data_in_1_IBUF,
      ADR2 => data_4_1,
      O => Mmux_n0006_Result_1_1_O
    );
  Mmux_n0006_Result_0_1_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0006_Result_0_1_O,
      O => Q_n0006(0)
    );
  Mmux_n0006_Result_0_1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => Q_n0052,
      ADR1 => data_in_0_IBUF,
      ADR2 => data_4_0,
      O => Mmux_n0006_Result_0_1_O
    );
  Mmux_n0007_Result_6_1_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0007_Result_6_1_O,
      O => Q_n0007(6)
    );
  Mmux_n0007_Result_6_1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => Q_n0054,
      ADR1 => data_in_6_IBUF,
      ADR2 => data_5_6,
      O => Mmux_n0007_Result_6_1_O
    );
  Mmux_n0007_Result_5_1_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0007_Result_5_1_O,
      O => Q_n0007(5)
    );
  Mmux_n0007_Result_5_1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => Q_n0054,
      ADR1 => data_in_5_IBUF,
      ADR2 => data_5_5,
      O => Mmux_n0007_Result_5_1_O
    );
  Mmux_n0007_Result_4_1_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0007_Result_4_1_O,
      O => Q_n0007(4)
    );
  Mmux_n0007_Result_4_1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => Q_n0054,
      ADR1 => data_in_4_IBUF,
      ADR2 => data_5_4,
      O => Mmux_n0007_Result_4_1_O
    );
  Mmux_n0007_Result_3_1_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0007_Result_3_1_O,
      O => Q_n0007(3)
    );
  Mmux_n0007_Result_3_1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => Q_n0054,
      ADR1 => data_in_3_IBUF,
      ADR2 => data_5_3,
      O => Mmux_n0007_Result_3_1_O
    );
  Mmux_n0007_Result_2_1_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0007_Result_2_1_O,
      O => Q_n0007(2)
    );
  Mmux_n0007_Result_2_1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => Q_n0054,
      ADR1 => data_in_2_IBUF,
      ADR2 => data_5_2,
      O => Mmux_n0007_Result_2_1_O
    );
  Mmux_n0007_Result_1_1_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0007_Result_1_1_O,
      O => Q_n0007(1)
    );
  Mmux_n0007_Result_1_1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => Q_n0054,
      ADR1 => data_in_1_IBUF,
      ADR2 => data_5_1,
      O => Mmux_n0007_Result_1_1_O
    );
  Mmux_n0007_Result_0_1_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0007_Result_0_1_O,
      O => Q_n0007(0)
    );
  Mmux_n0007_Result_0_1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => Q_n0054,
      ADR1 => data_in_0_IBUF,
      ADR2 => data_5_0,
      O => Mmux_n0007_Result_0_1_O
    );
  Mmux_n0008_Result_6_1_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0008_Result_6_1_O,
      O => Q_n0008(6)
    );
  Mmux_n0008_Result_6_1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => Q_n0056,
      ADR1 => data_in_6_IBUF,
      ADR2 => data_6_6,
      O => Mmux_n0008_Result_6_1_O
    );
  Mmux_n0008_Result_5_1_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0008_Result_5_1_O,
      O => Q_n0008(5)
    );
  Mmux_n0008_Result_5_1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => Q_n0056,
      ADR1 => data_in_5_IBUF,
      ADR2 => data_6_5,
      O => Mmux_n0008_Result_5_1_O
    );
  Mmux_n0008_Result_4_1_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0008_Result_4_1_O,
      O => Q_n0008(4)
    );
  Mmux_n0008_Result_4_1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => Q_n0056,
      ADR1 => data_in_4_IBUF,
      ADR2 => data_6_4,
      O => Mmux_n0008_Result_4_1_O
    );
  Mmux_n0008_Result_3_1_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0008_Result_3_1_O,
      O => Q_n0008(3)
    );
  Mmux_n0008_Result_3_1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => Q_n0056,
      ADR1 => data_in_3_IBUF,
      ADR2 => data_6_3,
      O => Mmux_n0008_Result_3_1_O
    );
  Mmux_n0008_Result_2_1_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0008_Result_2_1_O,
      O => Q_n0008(2)
    );
  Mmux_n0008_Result_2_1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => Q_n0056,
      ADR1 => data_in_2_IBUF,
      ADR2 => data_6_2,
      O => Mmux_n0008_Result_2_1_O
    );
  Mmux_n0008_Result_1_1_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0008_Result_1_1_O,
      O => Q_n0008(1)
    );
  Mmux_n0008_Result_1_1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => Q_n0056,
      ADR1 => data_in_1_IBUF,
      ADR2 => data_6_1,
      O => Mmux_n0008_Result_1_1_O
    );
  Mmux_n0008_Result_0_1_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0008_Result_0_1_O,
      O => Q_n0008(0)
    );
  Mmux_n0008_Result_0_1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => Q_n0056,
      ADR1 => data_in_0_IBUF,
      ADR2 => data_6_0,
      O => Mmux_n0008_Result_0_1_O
    );
  Mmux_n0009_Result_6_1_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0009_Result_6_1_O,
      O => Q_n0009(6)
    );
  Mmux_n0009_Result_6_1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => Q_n0019,
      ADR1 => data_7_6,
      ADR2 => data_in_6_IBUF,
      O => Mmux_n0009_Result_6_1_O
    );
  Mmux_n0009_Result_5_1_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0009_Result_5_1_O,
      O => Q_n0009(5)
    );
  Mmux_n0009_Result_5_1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => Q_n0019,
      ADR1 => data_7_5,
      ADR2 => data_in_5_IBUF,
      O => Mmux_n0009_Result_5_1_O
    );
  Mmux_n0009_Result_4_1_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0009_Result_4_1_O,
      O => Q_n0009(4)
    );
  Mmux_n0009_Result_4_1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => Q_n0019,
      ADR1 => data_7_4,
      ADR2 => data_in_4_IBUF,
      O => Mmux_n0009_Result_4_1_O
    );
  Mmux_n0009_Result_3_1_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0009_Result_3_1_O,
      O => Q_n0009(3)
    );
  Mmux_n0009_Result_3_1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => Q_n0019,
      ADR1 => data_7_3,
      ADR2 => data_in_3_IBUF,
      O => Mmux_n0009_Result_3_1_O
    );
  Mmux_n0009_Result_2_1_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0009_Result_2_1_O,
      O => Q_n0009(2)
    );
  Mmux_n0009_Result_2_1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => Q_n0019,
      ADR1 => data_7_2,
      ADR2 => data_in_2_IBUF,
      O => Mmux_n0009_Result_2_1_O
    );
  Mmux_n0009_Result_1_1_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0009_Result_1_1_O,
      O => Q_n0009(1)
    );
  Mmux_n0009_Result_1_1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => Q_n0019,
      ADR1 => data_7_1,
      ADR2 => data_in_1_IBUF,
      O => Mmux_n0009_Result_1_1_O
    );
  Mmux_n0009_Result_0_1_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0009_Result_0_1_O,
      O => Q_n0009(0)
    );
  Mmux_n0009_Result_0_1 : X_LUT3
    generic map(
      INIT =