my_sram_translate.vhd

FPGA系统的sram的软仿真设计

  Mmux_n0011_inst_lut3_201_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0011_inst_lut3_201_O,
      O => Mmux_n0011_net35
    );
  Mmux_n0011_inst_lut3_201 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => raddr_0_IBUF,
      ADR1 => data_0_5,
      ADR2 => data_1_5,
      O => Mmux_n0011_inst_lut3_201_O
    );
  Mmux_n0011_inst_lut3_191_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0011_inst_lut3_191_O,
      O => Mmux_n0011_net32
    );
  Mmux_n0011_inst_lut3_191 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => raddr_0_IBUF,
      ADR1 => data_6_4,
      ADR2 => data_7_4,
      O => Mmux_n0011_inst_lut3_191_O
    );
  Mmux_n0011_inst_lut3_181_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0011_inst_lut3_181_O,
      O => Mmux_n0011_net31
    );
  Mmux_n0011_inst_lut3_181 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => raddr_0_IBUF,
      ADR1 => data_4_4,
      ADR2 => data_5_4,
      O => Mmux_n0011_inst_lut3_181_O
    );
  Mmux_n0011_inst_lut3_171_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0011_inst_lut3_171_O,
      O => Mmux_n0011_net29
    );
  Mmux_n0011_inst_lut3_171 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => raddr_0_IBUF,
      ADR1 => data_2_4,
      ADR2 => data_3_4,
      O => Mmux_n0011_inst_lut3_171_O
    );
  Mmux_n0011_inst_lut3_161_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0011_inst_lut3_161_O,
      O => Mmux_n0011_net28
    );
  Mmux_n0011_inst_lut3_161 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => raddr_0_IBUF,
      ADR1 => data_0_4,
      ADR2 => data_1_4,
      O => Mmux_n0011_inst_lut3_161_O
    );
  Mmux_n0011_inst_lut3_151_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0011_inst_lut3_151_O,
      O => Mmux_n0011_net25
    );
  Mmux_n0011_inst_lut3_151 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => raddr_0_IBUF,
      ADR1 => data_6_3,
      ADR2 => data_7_3,
      O => Mmux_n0011_inst_lut3_151_O
    );
  Mmux_n0011_inst_lut3_141_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0011_inst_lut3_141_O,
      O => Mmux_n0011_net24
    );
  Mmux_n0011_inst_lut3_141 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => raddr_0_IBUF,
      ADR1 => data_4_3,
      ADR2 => data_5_3,
      O => Mmux_n0011_inst_lut3_141_O
    );
  Mmux_n0011_inst_lut3_131_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0011_inst_lut3_131_O,
      O => Mmux_n0011_net22
    );
  Mmux_n0011_inst_lut3_131 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => raddr_0_IBUF,
      ADR1 => data_2_3,
      ADR2 => data_3_3,
      O => Mmux_n0011_inst_lut3_131_O
    );
  Mmux_n0011_inst_lut3_121_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0011_inst_lut3_121_O,
      O => Mmux_n0011_net21
    );
  Mmux_n0011_inst_lut3_121 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => raddr_0_IBUF,
      ADR1 => data_0_3,
      ADR2 => data_1_3,
      O => Mmux_n0011_inst_lut3_121_O
    );
  Mmux_n0011_inst_lut3_111_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0011_inst_lut3_111_O,
      O => Mmux_n0011_net18
    );
  Mmux_n0011_inst_lut3_111 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => raddr_0_IBUF,
      ADR1 => data_6_2,
      ADR2 => data_7_2,
      O => Mmux_n0011_inst_lut3_111_O
    );
  Mmux_n0011_inst_lut3_101_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0011_inst_lut3_101_O,
      O => Mmux_n0011_net17
    );
  Mmux_n0011_inst_lut3_101 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => raddr_0_IBUF,
      ADR1 => data_4_2,
      ADR2 => data_5_2,
      O => Mmux_n0011_inst_lut3_101_O
    );
  Mmux_n0011_inst_lut3_91_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0011_inst_lut3_91_O,
      O => Mmux_n0011_net15
    );
  Mmux_n0011_inst_lut3_91 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => raddr_0_IBUF,
      ADR1 => data_2_2,
      ADR2 => data_3_2,
      O => Mmux_n0011_inst_lut3_91_O
    );
  Mmux_n0011_inst_lut3_81_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0011_inst_lut3_81_O,
      O => Mmux_n0011_net14
    );
  Mmux_n0011_inst_lut3_81 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => raddr_0_IBUF,
      ADR1 => data_0_2,
      ADR2 => data_1_2,
      O => Mmux_n0011_inst_lut3_81_O
    );
  Mmux_n0011_inst_lut3_71_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0011_inst_lut3_71_O,
      O => Mmux_n0011_net11
    );
  Mmux_n0011_inst_lut3_71 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => raddr_0_IBUF,
      ADR1 => data_6_1,
      ADR2 => data_7_1,
      O => Mmux_n0011_inst_lut3_71_O
    );
  Mmux_n0011_inst_lut3_61_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0011_inst_lut3_61_O,
      O => Mmux_n0011_net10
    );
  Mmux_n0011_inst_lut3_61 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => raddr_0_IBUF,
      ADR1 => data_4_1,
      ADR2 => data_5_1,
      O => Mmux_n0011_inst_lut3_61_O
    );
  Mmux_n0011_inst_lut3_51_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0011_inst_lut3_51_O,
      O => Mmux_n0011_net8
    );
  Mmux_n0011_inst_lut3_51 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => raddr_0_IBUF,
      ADR1 => data_2_1,
      ADR2 => data_3_1,
      O => Mmux_n0011_inst_lut3_51_O
    );
  Mmux_n0011_inst_lut3_41_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0011_inst_lut3_41_O,
      O => Mmux_n0011_net7
    );
  Mmux_n0011_inst_lut3_41 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => raddr_0_IBUF,
      ADR1 => data_0_1,
      ADR2 => data_1_1,
      O => Mmux_n0011_inst_lut3_41_O
    );
  Mmux_n0011_inst_lut3_32_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0011_inst_lut3_32_O,
      O => Mmux_n0011_net4
    );
  Mmux_n0011_inst_lut3_32 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => raddr_0_IBUF,
      ADR1 => data_6_0,
      ADR2 => data_7_0,
      O => Mmux_n0011_inst_lut3_32_O
    );
  Mmux_n0011_inst_lut3_210_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0011_inst_lut3_210_O,
      O => Mmux_n0011_net3
    );
  Mmux_n0011_inst_lut3_210 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => raddr_0_IBUF,
      ADR1 => data_4_0,
      ADR2 => data_5_0,
      O => Mmux_n0011_inst_lut3_210_O
    );
  Mmux_n0011_inst_lut3_110_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0011_inst_lut3_110_O,
      O => Mmux_n0011_net1
    );
  Mmux_n0011_inst_lut3_110 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => raddr_0_IBUF,
      ADR1 => data_2_0,
      ADR2 => data_3_0,
      O => Mmux_n0011_inst_lut3_110_O
    );
  Mmux_n0011_inst_lut3_01_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0011_inst_lut3_01_O,
      O => Mmux_n0011_net0
    );
  Mmux_n0011_inst_lut3_01 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => raddr_0_IBUF,
      ADR1 => data_0_0,
      ADR2 => data_1_0,
      O => Mmux_n0011_inst_lut3_01_O
    );
  Mmux_n0002_Result_6_1_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0002_Result_6_1_O,
      O => Q_n0002(6)
    );
  Mmux_n0002_Result_6_1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => Q_n0044,
      ADR1 => data_in_6_IBUF,
      ADR2 => data_0_6,
      O => Mmux_n0002_Result_6_1_O
    );
  Mmux_n0002_Result_5_1_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0002_Result_5_1_O,
      O => Q_n0002(5)
    );
  Mmux_n0002_Result_5_1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => Q_n0044,
      ADR1 => data_in_5_IBUF,
      ADR2 => data_0_5,
      O => Mmux_n0002_Result_5_1_O
    );
  Mmux_n0002_Result_4_1_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0002_Result_4_1_O,
      O => Q_n0002(4)
    );
  Mmux_n0002_Result_4_1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => Q_n0044,
      ADR1 => data_in_4_IBUF,
      ADR2 => data_0_4,
      O => Mmux_n0002_Result_4_1_O
    );
  Mmux_n0002_Result_3_1_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0002_Result_3_1_O,
      O => Q_n0002(3)
    );
  Mmux_n0002_Result_3_1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => Q_n0044,
      ADR1 => data_in_3_IBUF,
      ADR2 => data_0_3,
      O => Mmux_n0002_Result_3_1_O
    );
  Mmux_n0002_Result_2_1_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0002_Result_2_1_O,
      O => Q_n0002(2)
    );
  Mmux_n0002_Result_2_1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => Q_n0044,
      ADR1 => data_in_2_IBUF,
      ADR2 => data_0_2,
      O => Mmux_n0002_Result_2_1_O
    );
  Mmux_n0002_Result_1_1_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0002_Result_1_1_O,
      O => Q_n0002(1)
    );
  Mmux_n0002_Result_1_1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => Q_n0044,
      ADR1 => data_in_1_IBUF,
      ADR2 => data_0_1,
      O => Mmux_n0002_Result_1_1_O
    );
  Mmux_n0002_Result_0_1_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0002_Result_0_1_O,
      O => Q_n0002(0)
    );
  Mmux_n0002_Result_0_1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => Q_n0044,
      ADR1 => data_in_0_IBUF,
      ADR2 => data_0_0,
      O => Mmux_n0002_Result_0_1_O
    );
  Mmux_n0003_Result_6_1_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0003_Result_6_1_O,
      O => Q_n0003(6)
    );
  Mmux_n0003_Result_6_1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => Q_n0046,
      ADR1 => data_in_6_IBUF,
      ADR2 => data_1_6,
      O => Mmux_n0003_Result_6_1_O
    );
  Mmux_n0003_Result_5_1_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0003_Result_5_1_O,
      O => Q_n0003(5)
    );
  Mmux_n0003_Result_5_1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => Q_n0046,
      ADR1 => data_in_5_IBUF,
      ADR2 => data_1_5,
      O => Mmux_n0003_Result_5_1_O
    );
  Mmux_n0003_Result_4_1_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0003_Result_4_1_O,
      O => Q_n0003(4)
    );
  Mmux_n0003_Result_4_1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => Q_n0046,
      ADR1 => data_in_4_IBUF,
      ADR2 => data_1_4,
      O => Mmux_n0003_Result_4_1_O
    );
  Mmux_n0003_Result_3_1_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0003_Result_3_1_O,
      O => Q_n0003(3)
    );
  Mmux_n0003_Result_3_1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => Q_n0046,
      ADR1 => data_in_3_IBUF,
      ADR2 => data_1_3,
      O => Mmux_n0003_Result_3_1_O
    );
  Mmux_n0003_Result_2_1_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0003_Result_2_1_O,
      O => Q_n0003(2)
    );
  Mmux_n0003_Result_2_1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => Q_n0046,
      ADR1 => data_in_2_IBUF,
      ADR2 => data_1_2,
      O => Mmux_n0003_Result_2_1_O
    );
  Mmux_n0003_Result_1_1_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0003_Result_1_1_O,
      O => Q_n0003(1)
    );
  Mmux_n0003_Result_1_1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => Q_n0046,
      ADR1 => data_in_1_IBUF,
      ADR2 => data_1_1,
      O => Mmux_n0003_Result_1_1_O
    );
  Mmux_n0003_Result_0_1_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0003_Result_0_1_O,
      O => Q_n0003(0)
    );
  Mmux_n0003_Result_0_1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => Q_n0046,
      ADR1 => data_in_0_IBUF,
      ADR2 => data_1_0,
      O => Mmux_n0003_Result_0_1_O
    );
  Mmux_n0004_Result_6_1_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0004_Result_6_1_O,
      O => Q_n0004(6)
    );
  Mmux_n0004_Result_6_1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => Q_n0048,
      ADR1 => data_in_6_IBUF,
      ADR2 => data_2_6,
      O => Mmux_n0004_Result_6_1_O
    );
  Mmux_n0004_Result_5_1_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0004_Result_5_1_O,
      O => Q_n0004(5)
    );
  Mmux_n0004_Result_5_1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => Q_n0048,
      ADR1 => data_in_5_IBUF,
      ADR2 => data_2_5,
      O => Mmux_n0004_Result_5_1_O
    );
  Mmux_n0004_Result_4_1_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0004_Result_4_1_O,
      O => Q_n0004(4)
    );
  Mmux_n0004_Result_4_1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => Q_n0048,
      ADR1 => data_in_4_IBUF,
      ADR2 => data_2_4,
      O => Mmux_n0004_Result_4_1_O
    );
  Mmux_n0004_Result_3_1_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0004_Result_3_1_O,
      O => Q_n0004(3)