my_sram_translate.vhd

FPGA系统的sram的软仿真设计

    port map (
      I => Q_n0005(6),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_3_6,
      SET => GND,
      RST => GSR
    );
  data_2_0_62 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0004(0),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_2_0,
      SET => GND,
      RST => GSR
    );
  data_2_1_63 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0004(1),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_2_1,
      SET => GND,
      RST => GSR
    );
  data_2_2_64 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0004(2),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_2_2,
      SET => GND,
      RST => GSR
    );
  data_2_3_65 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0004(3),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_2_3,
      SET => GND,
      RST => GSR
    );
  data_2_4_66 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0004(4),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_2_4,
      SET => GND,
      RST => GSR
    );
  data_2_5_67 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0004(5),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_2_5,
      SET => GND,
      RST => GSR
    );
  data_2_6_68 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0004(6),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_2_6,
      SET => GND,
      RST => GSR
    );
  data_1_0_69 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0003(0),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_1_0,
      SET => GND,
      RST => GSR
    );
  data_1_1_70 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0003(1),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_1_1,
      SET => GND,
      RST => GSR
    );
  data_1_2_71 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0003(2),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_1_2,
      SET => GND,
      RST => GSR
    );
  data_out_0_OBUF : X_BUF
    port map (
      I => data_out_0,
      O => data_out_0_OBUF_GTS_TRI
    );
  data_out_1_OBUF : X_BUF
    port map (
      I => data_out_1,
      O => data_out_1_OBUF_GTS_TRI
    );
  Mmux_n0011_inst_mux_f5_0 : X_MUX2
    port map (
      IA => Mmux_n0011_net0,
      IB => Mmux_n0011_net1,
      SEL => raddr_1_IBUF,
      O => Mmux_n0011_net2
    );
  Mmux_n0011_inst_mux_f5_1 : X_MUX2
    port map (
      IA => Mmux_n0011_net3,
      IB => Mmux_n0011_net4,
      SEL => raddr_1_IBUF,
      O => Mmux_n0011_net5
    );
  Mmux_n0011_inst_mux_f6_0 : X_MUX2
    port map (
      IA => Mmux_n0011_net2,
      IB => Mmux_n0011_net5,
      SEL => raddr_2_IBUF,
      O => Q_n0011(0)
    );
  Mmux_n0011_inst_mux_f5_2 : X_MUX2
    port map (
      IA => Mmux_n0011_net7,
      IB => Mmux_n0011_net8,
      SEL => raddr_1_IBUF,
      O => Mmux_n0011_net9
    );
  Mmux_n0011_inst_mux_f5_3 : X_MUX2
    port map (
      IA => Mmux_n0011_net10,
      IB => Mmux_n0011_net11,
      SEL => raddr_1_IBUF,
      O => Mmux_n0011_net12
    );
  Mmux_n0011_inst_mux_f6_1 : X_MUX2
    port map (
      IA => Mmux_n0011_net9,
      IB => Mmux_n0011_net12,
      SEL => raddr_2_IBUF,
      O => Q_n0011(1)
    );
  Mmux_n0011_inst_mux_f5_4 : X_MUX2
    port map (
      IA => Mmux_n0011_net14,
      IB => Mmux_n0011_net15,
      SEL => raddr_1_IBUF,
      O => Mmux_n0011_net16
    );
  Mmux_n0011_inst_mux_f5_5 : X_MUX2
    port map (
      IA => Mmux_n0011_net17,
      IB => Mmux_n0011_net18,
      SEL => raddr_1_IBUF,
      O => Mmux_n0011_net19
    );
  Mmux_n0011_inst_mux_f6_2 : X_MUX2
    port map (
      IA => Mmux_n0011_net16,
      IB => Mmux_n0011_net19,
      SEL => raddr_2_IBUF,
      O => Q_n0011(2)
    );
  Mmux_n0011_inst_mux_f5_6 : X_MUX2
    port map (
      IA => Mmux_n0011_net21,
      IB => Mmux_n0011_net22,
      SEL => raddr_1_IBUF,
      O => Mmux_n0011_net23
    );
  Mmux_n0011_inst_mux_f5_7 : X_MUX2
    port map (
      IA => Mmux_n0011_net24,
      IB => Mmux_n0011_net25,
      SEL => raddr_1_IBUF,
      O => Mmux_n0011_net26
    );
  Mmux_n0011_inst_mux_f6_3 : X_MUX2
    port map (
      IA => Mmux_n0011_net23,
      IB => Mmux_n0011_net26,
      SEL => raddr_2_IBUF,
      O => Q_n0011(3)
    );
  Mmux_n0011_inst_mux_f5_8 : X_MUX2
    port map (
      IA => Mmux_n0011_net28,
      IB => Mmux_n0011_net29,
      SEL => raddr_1_IBUF,
      O => Mmux_n0011_net30
    );
  Mmux_n0011_inst_mux_f5_9 : X_MUX2
    port map (
      IA => Mmux_n0011_net31,
      IB => Mmux_n0011_net32,
      SEL => raddr_1_IBUF,
      O => Mmux_n0011_net33
    );
  Mmux_n0011_inst_mux_f6_4 : X_MUX2
    port map (
      IA => Mmux_n0011_net30,
      IB => Mmux_n0011_net33,
      SEL => raddr_2_IBUF,
      O => Q_n0011(4)
    );
  Mmux_n0011_inst_mux_f5_10 : X_MUX2
    port map (
      IA => Mmux_n0011_net35,
      IB => Mmux_n0011_net36,
      SEL => raddr_1_IBUF,
      O => Mmux_n0011_net37
    );
  Mmux_n0011_inst_mux_f5_11 : X_MUX2
    port map (
      IA => Mmux_n0011_net38,
      IB => Mmux_n0011_net39,
      SEL => raddr_1_IBUF,
      O => Mmux_n0011_net40
    );
  Mmux_n0011_inst_mux_f6_5 : X_MUX2
    port map (
      IA => Mmux_n0011_net37,
      IB => Mmux_n0011_net40,
      SEL => raddr_2_IBUF,
      O => Q_n0011(5)
    );
  Mmux_n0011_inst_mux_f5_12 : X_MUX2
    port map (
      IA => Mmux_n0011_net42,
      IB => Mmux_n0011_net43,
      SEL => raddr_1_IBUF,
      O => Mmux_n0011_net44
    );
  Mmux_n0011_inst_mux_f5_13 : X_MUX2
    port map (
      IA => Mmux_n0011_net45,
      IB => Mmux_n0011_net46,
      SEL => raddr_1_IBUF,
      O => Mmux_n0011_net47
    );
  Mmux_n0011_inst_mux_f6_6 : X_MUX2
    port map (
      IA => Mmux_n0011_net44,
      IB => Mmux_n0011_net47,
      SEL => raddr_2_IBUF,
      O => Q_n0011(6)
    );
  Mmux_n0011_inst_mux_f5_14 : X_MUX2
    port map (
      IA => Mmux_n0011_net49,
      IB => Mmux_n0011_net50,
      SEL => raddr_1_IBUF,
      O => Mmux_n0011_net51
    );
  Mmux_n0011_inst_mux_f5_15 : X_MUX2
    port map (
      IA => Mmux_n0011_net52,
      IB => Mmux_n0011_net53,
      SEL => raddr_1_IBUF,
      O => Mmux_n0011_net54
    );
  re_IBUF_72 : X_BUF
    port map (
      I => re,
      O => re_IBUF
    );
  we_IBUF_73 : X_BUF
    port map (
      I => we,
      O => we_IBUF
    );
  data_in_7_IBUF_74 : X_BUF
    port map (
      I => data_in(7),
      O => data_in_7_IBUF
    );
  data_in_6_IBUF_75 : X_BUF
    port map (
      I => data_in(6),
      O => data_in_6_IBUF
    );
  data_in_5_IBUF_76 : X_BUF
    port map (
      I => data_in(5),
      O => data_in_5_IBUF
    );
  data_in_4_IBUF_77 : X_BUF
    port map (
      I => data_in(4),
      O => data_in_4_IBUF
    );
  data_in_3_IBUF_78 : X_BUF
    port map (
      I => data_in(3),
      O => data_in_3_IBUF
    );
  data_in_2_IBUF_79 : X_BUF
    port map (
      I => data_in(2),
      O => data_in_2_IBUF
    );
  data_in_1_IBUF_80 : X_BUF
    port map (
      I => data_in(1),
      O => data_in_1_IBUF
    );
  data_in_0_IBUF_81 : X_BUF
    port map (
      I => data_in(0),
      O => data_in_0_IBUF
    );
  raddr_2_IBUF_82 : X_BUF
    port map (
      I => raddr(2),
      O => raddr_2_IBUF
    );
  raddr_1_IBUF_83 : X_BUF
    port map (
      I => raddr(1),
      O => raddr_1_IBUF
    );
  raddr_0_IBUF_84 : X_BUF
    port map (
      I => raddr(0),
      O => raddr_0_IBUF
    );
  waddr_2_IBUF_85 : X_BUF
    port map (
      I => waddr(2),
      O => waddr_2_IBUF
    );
  waddr_1_IBUF_86 : X_BUF
    port map (
      I => waddr(1),
      O => waddr_1_IBUF
    );
  waddr_0_IBUF_87 : X_BUF
    port map (
      I => waddr(0),
      O => waddr_0_IBUF
    );
  data_out_7_OBUF : X_BUF
    port map (
      I => data_out_7,
      O => data_out_7_OBUF_GTS_TRI
    );
  data_out_6_OBUF : X_BUF
    port map (
      I => data_out_6,
      O => data_out_6_OBUF_GTS_TRI
    );
  data_out_5_OBUF : X_BUF
    port map (
      I => data_out_5,
      O => data_out_5_OBUF_GTS_TRI
    );
  data_out_4_OBUF : X_BUF
    port map (
      I => data_out_4,
      O => data_out_4_OBUF_GTS_TRI
    );
  data_out_3_OBUF : X_BUF
    port map (
      I => data_out_3,
      O => data_out_3_OBUF_GTS_TRI
    );
  data_out_2_OBUF : X_BUF
    port map (
      I => data_out_2,
      O => data_out_2_OBUF_GTS_TRI
    );
  Mmux_n0011_inst_lut3_311_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0011_inst_lut3_311_O,
      O => Mmux_n0011_net53
    );
  Mmux_n0011_inst_lut3_311 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => raddr_0_IBUF,
      ADR1 => data_6_7,
      ADR2 => data_7_7,
      O => Mmux_n0011_inst_lut3_311_O
    );
  Mmux_n0011_inst_lut3_301_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0011_inst_lut3_301_O,
      O => Mmux_n0011_net52
    );
  Mmux_n0011_inst_lut3_301 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => raddr_0_IBUF,
      ADR1 => data_4_7,
      ADR2 => data_5_7,
      O => Mmux_n0011_inst_lut3_301_O
    );
  Mmux_n0011_inst_lut3_291_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0011_inst_lut3_291_O,
      O => Mmux_n0011_net50
    );
  Mmux_n0011_inst_lut3_291 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => raddr_0_IBUF,
      ADR1 => data_2_7,
      ADR2 => data_3_7,
      O => Mmux_n0011_inst_lut3_291_O
    );
  Mmux_n0011_inst_lut3_281_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0011_inst_lut3_281_O,
      O => Mmux_n0011_net49
    );
  Mmux_n0011_inst_lut3_281 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => raddr_0_IBUF,
      ADR1 => data_0_7,
      ADR2 => data_1_7,
      O => Mmux_n0011_inst_lut3_281_O
    );
  Mmux_n0011_inst_lut3_271_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0011_inst_lut3_271_O,
      O => Mmux_n0011_net46
    );
  Mmux_n0011_inst_lut3_271 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => raddr_0_IBUF,
      ADR1 => data_6_6,
      ADR2 => data_7_6,
      O => Mmux_n0011_inst_lut3_271_O
    );
  Mmux_n0011_inst_lut3_261_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0011_inst_lut3_261_O,
      O => Mmux_n0011_net45
    );
  Mmux_n0011_inst_lut3_261 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => raddr_0_IBUF,
      ADR1 => data_4_6,
      ADR2 => data_5_6,
      O => Mmux_n0011_inst_lut3_261_O
    );
  Mmux_n0011_inst_lut3_251_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0011_inst_lut3_251_O,
      O => Mmux_n0011_net43
    );
  Mmux_n0011_inst_lut3_251 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => raddr_0_IBUF,
      ADR1 => data_2_6,
      ADR2 => data_3_6,
      O => Mmux_n0011_inst_lut3_251_O
    );
  Mmux_n0011_inst_lut3_241_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0011_inst_lut3_241_O,
      O => Mmux_n0011_net42
    );
  Mmux_n0011_inst_lut3_241 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => raddr_0_IBUF,
      ADR1 => data_0_6,
      ADR2 => data_1_6,
      O => Mmux_n0011_inst_lut3_241_O
    );
  Mmux_n0011_inst_lut3_231_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0011_inst_lut3_231_O,
      O => Mmux_n0011_net39
    );
  Mmux_n0011_inst_lut3_231 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => raddr_0_IBUF,
      ADR1 => data_6_5,
      ADR2 => data_7_5,
      O => Mmux_n0011_inst_lut3_231_O
    );
  Mmux_n0011_inst_lut3_221_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0011_inst_lut3_221_O,
      O => Mmux_n0011_net38
    );
  Mmux_n0011_inst_lut3_221 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => raddr_0_IBUF,
      ADR1 => data_4_5,
      ADR2 => data_5_5,
      O => Mmux_n0011_inst_lut3_221_O
    );
  Mmux_n0011_inst_lut3_211_LUT3_L_BUF : X_BUF
    port map (
      I => Mmux_n0011_inst_lut3_211_O,
      O => Mmux_n0011_net36
    );
  Mmux_n0011_inst_lut3_211 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => raddr_0_IBUF,
      ADR1 => data_2_5,
      ADR2 => data_3_5,
      O => Mmux_n0011_inst_lut3_211_O
    );