my_sram_translate.vhd

FPGA系统的sram的软仿真设计

      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_2_7,
      SET => GND,
      RST => GSR
    );
  data_3_7_14 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0005(7),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_3_7,
      SET => GND,
      RST => GSR
    );
  data_4_7_15 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0006(7),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_4_7,
      SET => GND,
      RST => GSR
    );
  data_5_7_16 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0007(7),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_5_7,
      SET => GND,
      RST => GSR
    );
  data_6_7_17 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0008(7),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_6_7,
      SET => GND,
      RST => GSR
    );
  data_7_7_18 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0009(7),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_7_7,
      SET => GND,
      RST => GSR
    );
  data_out_7_19 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0011(7),
      CE => Q_n0040,
      CLK => clock_BUFGP,
      O => data_out_7,
      SET => GND,
      RST => GSR
    );
  data_out_0_20 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0011(0),
      CE => Q_n0040,
      CLK => clock_BUFGP,
      O => data_out_0,
      SET => GND,
      RST => GSR
    );
  data_out_1_21 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0011(1),
      CE => Q_n0040,
      CLK => clock_BUFGP,
      O => data_out_1,
      SET => GND,
      RST => GSR
    );
  data_out_2_22 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0011(2),
      CE => Q_n0040,
      CLK => clock_BUFGP,
      O => data_out_2,
      SET => GND,
      RST => GSR
    );
  data_out_3_23 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0011(3),
      CE => Q_n0040,
      CLK => clock_BUFGP,
      O => data_out_3,
      SET => GND,
      RST => GSR
    );
  data_out_4_24 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0011(4),
      CE => Q_n0040,
      CLK => clock_BUFGP,
      O => data_out_4,
      SET => GND,
      RST => GSR
    );
  data_out_5_25 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0011(5),
      CE => Q_n0040,
      CLK => clock_BUFGP,
      O => data_out_5,
      SET => GND,
      RST => GSR
    );
  data_out_6_26 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0011(6),
      CE => Q_n0040,
      CLK => clock_BUFGP,
      O => data_out_6,
      SET => GND,
      RST => GSR
    );
  data_7_0_27 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0009(0),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_7_0,
      SET => GND,
      RST => GSR
    );
  data_7_1_28 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0009(1),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_7_1,
      SET => GND,
      RST => GSR
    );
  data_7_2_29 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0009(2),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_7_2,
      SET => GND,
      RST => GSR
    );
  data_7_3_30 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0009(3),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_7_3,
      SET => GND,
      RST => GSR
    );
  data_7_4_31 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0009(4),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_7_4,
      SET => GND,
      RST => GSR
    );
  data_7_5_32 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0009(5),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_7_5,
      SET => GND,
      RST => GSR
    );
  data_7_6_33 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0009(6),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_7_6,
      SET => GND,
      RST => GSR
    );
  data_6_0_34 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0008(0),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_6_0,
      SET => GND,
      RST => GSR
    );
  data_6_1_35 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0008(1),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_6_1,
      SET => GND,
      RST => GSR
    );
  data_6_2_36 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0008(2),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_6_2,
      SET => GND,
      RST => GSR
    );
  data_6_3_37 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0008(3),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_6_3,
      SET => GND,
      RST => GSR
    );
  data_6_4_38 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0008(4),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_6_4,
      SET => GND,
      RST => GSR
    );
  data_6_5_39 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0008(5),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_6_5,
      SET => GND,
      RST => GSR
    );
  data_6_6_40 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0008(6),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_6_6,
      SET => GND,
      RST => GSR
    );
  data_5_0_41 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0007(0),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_5_0,
      SET => GND,
      RST => GSR
    );
  data_5_1_42 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0007(1),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_5_1,
      SET => GND,
      RST => GSR
    );
  data_5_2_43 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0007(2),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_5_2,
      SET => GND,
      RST => GSR
    );
  data_5_3_44 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0007(3),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_5_3,
      SET => GND,
      RST => GSR
    );
  data_5_4_45 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0007(4),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_5_4,
      SET => GND,
      RST => GSR
    );
  data_5_5_46 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0007(5),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_5_5,
      SET => GND,
      RST => GSR
    );
  data_5_6_47 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0007(6),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_5_6,
      SET => GND,
      RST => GSR
    );
  data_4_0_48 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0006(0),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_4_0,
      SET => GND,
      RST => GSR
    );
  data_4_1_49 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0006(1),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_4_1,
      SET => GND,
      RST => GSR
    );
  data_4_2_50 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0006(2),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_4_2,
      SET => GND,
      RST => GSR
    );
  data_4_3_51 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0006(3),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_4_3,
      SET => GND,
      RST => GSR
    );
  data_4_4_52 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0006(4),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_4_4,
      SET => GND,
      RST => GSR
    );
  data_4_5_53 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0006(5),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_4_5,
      SET => GND,
      RST => GSR
    );
  data_4_6_54 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0006(6),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_4_6,
      SET => GND,
      RST => GSR
    );
  data_3_0_55 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0005(0),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_3_0,
      SET => GND,
      RST => GSR
    );
  data_3_1_56 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0005(1),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_3_1,
      SET => GND,
      RST => GSR
    );
  data_3_2_57 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0005(2),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_3_2,
      SET => GND,
      RST => GSR
    );
  data_3_3_58 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0005(3),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_3_3,
      SET => GND,
      RST => GSR
    );
  data_3_4_59 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0005(4),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_3_4,
      SET => GND,
      RST => GSR
    );
  data_3_5_60 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0005(5),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_3_5,
      SET => GND,
      RST => GSR
    );
  data_3_6_61 : X_FF
    generic map(
      INIT => '0'
    )